From 209a765a09c2de8f24ffb0b8c78ccddac64bb849 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 10 Jan 2019 21:50:07 +0300 Subject: [PATCH 092/122] LVDS: AR0231: add rev6,rev4 on max9286 This reenables support on MAX9286 Signed-off-by: Vladimir Barinov --- drivers/media/i2c/soc_camera/ar0231.c | 16 +- drivers/media/i2c/soc_camera/ar0231.h | 7 +- drivers/media/i2c/soc_camera/ar0231_rev4.h | 38 ++-- drivers/media/i2c/soc_camera/ar0231_rev6.h | 343 +++++++++++++++++++++++++++++ drivers/media/i2c/soc_camera/ar0231_rev7.h | 77 ++++--- 5 files changed, 427 insertions(+), 54 deletions(-) create mode 100644 drivers/media/i2c/soc_camera/ar0231_rev6.h diff --git a/drivers/media/i2c/soc_camera/ar0231.c b/drivers/media/i2c/soc_camera/ar0231.c index f575cb7..07f2b5e 100644 --- a/drivers/media/i2c/soc_camera/ar0231.c +++ b/drivers/media/i2c/soc_camera/ar0231.c @@ -20,11 +20,12 @@ #include #include -#include "ar0231_rev7.h" +#include "ar0231.h" static const int ar0231_i2c_addr[] = {0x10, 0x20}; #define AR0231_PID 0x3000 +#define AR0231_REV 0x300E #define AR0231_VERSION_REG 0x0354 #define AR0231_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGRBG12_1X12 @@ -393,7 +394,7 @@ static int ar0231_initialize(struct i2c_client *client) { struct ar0231_priv *priv = to_ar0231(client); u16 val = 0; - u16 pid = 0; + u16 pid = 0, rev = 0; int ret = 0; int tmp_addr; int i; @@ -425,18 +426,23 @@ static int ar0231_initialize(struct i2c_client *client) goto err; } + /* check revision */ + reg16_read16(client, AR0231_REV, &rev); /* Read OTP IDs */ ar0231_otp_id_read(client); /* Program wizard registers */ - ar0231_set_regs(client, ar0231_regs_wizard_rev7, ARRAY_SIZE(ar0231_regs_wizard_rev7)); + if (priv->ti9x4_addr) + ar0231_set_regs(client, ar0231_regs_wizard_rev7, ARRAY_SIZE(ar0231_regs_wizard_rev7)); + if (priv->max9286_addr) + ar0231_set_regs(client, ar0231_regs_wizard_rev6_dvp, ARRAY_SIZE(ar0231_regs_wizard_rev6_dvp)); /* Enable stream */ reg16_read16(client, 0x301a, &val); val |= (1 << 2); reg16_write16(client, 0x301a, val); - dev_info(&client->dev, "ar0231 PID %x, res %dx%d, OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n", - pid, AR0231_MAX_WIDTH, AR0231_MAX_HEIGHT, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); + dev_info(&client->dev, "ar0231 PID %x (rev %x), res %dx%d, OTP_ID %02x:%02x:%02x:%02x:%02x:%02x\n", + pid, rev, AR0231_MAX_WIDTH, AR0231_MAX_HEIGHT, priv->id[0], priv->id[1], priv->id[2], priv->id[3], priv->id[4], priv->id[5]); err: ar0231_s_port(client, 0); return ret; diff --git a/drivers/media/i2c/soc_camera/ar0231.h b/drivers/media/i2c/soc_camera/ar0231.h index b63dc91..09fc7d2d 100644 --- a/drivers/media/i2c/soc_camera/ar0231.h +++ b/drivers/media/i2c/soc_camera/ar0231.h @@ -12,8 +12,8 @@ //#define AR0231_DISPLAY_PATTERN_FIXED //#define AR0231_DISPLAY_PATTERN_COLOR_BAR -#define AR0231_MAX_WIDTH 1928 -#define AR0231_MAX_HEIGHT 1208 +#define AR0231_MAX_WIDTH 1920 +#define AR0231_MAX_HEIGHT 1200 #define AR0231_DELAY 0xffff @@ -31,4 +31,5 @@ struct ar0231_reg { }; #include "ar0231_rev4.h" -//#include "ar0231_rev6.h" +#include "ar0231_rev6.h" +#include "ar0231_rev7.h" diff --git a/drivers/media/i2c/soc_camera/ar0231_rev4.h b/drivers/media/i2c/soc_camera/ar0231_rev4.h index d4614ec..0627d96 100644 --- a/drivers/media/i2c/soc_camera/ar0231_rev4.h +++ b/drivers/media/i2c/soc_camera/ar0231_rev4.h @@ -9,7 +9,7 @@ * option) any later version. */ -static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { +static const struct ar0231_reg ar0231_regs_wizard_rev4_dvp[] = { {0x301A, 0x0001}, // reset {0x301A, 0x10D8}, // Stream off and setup parallel {0x3070, 0x0000}, // 1: Solid color test pattern, @@ -26,6 +26,7 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { #ifdef AR0231_DISPLAY_PATTERN_COLOR_BAR {0x3070, 0x0002}, #endif + //Recommended Settings {0x3366, 0x6666}, // ANALOG_GAIN {0x3056, 0x0080}, // GREEN1_GAIN @@ -116,6 +117,7 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { {0x3566, 0x1128}, // RESERVED_MFR_3566 {0x3566, 0x1328}, // RESERVED_MFR_3566 {0x3566, 0x3328}, // RESERVED_MFR_3566 + //Sequencer Update {0x2512, 0x8000}, // SEQ_CTRL_PORT {0x2510, 0x0905}, // SEQ_DATA_PORT @@ -251,6 +253,7 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { {0x32D4, 0x3702}, // RESERVED_MFR_32D4 {0x32D6, 0x3C04}, // RESERVED_MFR_32D6 {0x32DC, 0x370A}, // RESERVED_MFR_32DC + //Parallel Timing Setup {0x302A, 0x0009}, // VT_PIX_CLK_DIV {0x302C, 0x0001}, // VT_SYS_CLK_DIV @@ -259,21 +262,20 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { {0x3036, 0x0008}, // OP_WORD_CLK_DIV {0x3038, 0x0001}, // OP_SYS_CLK_DIV {0x30B0, 0x0A00}, // DIGITAL_TEST + //Readout Mode Configuration {0x30A2, 0x0001}, // X_ODD_INC_ {0x30A6, 0x0001}, // Y_ODD_INC_ {0x3040, 0x0000}, // READ_MODE {0x3044, 0x0400}, // DARK_CONTROL -{0x33E0, 0x0880}, // RESERVED_MFR_33E0 -{0x3180, 0x0080}, // RESERVED_MFR_3180 -{0x33E4, 0x0080}, // RESERVED_MFR_33E4 - -//HDR Readout Mode Configuration #ifdef AR0231_EMBEDDED_LINE {0x3064, 0x1982}, // SMIA_TEST #else {0x3064, 0x1802}, // SMIA_TEST #endif +{0x33E0, 0x0880}, // RESERVED_MFR_33E0 +{0x3180, 0x0080}, // RESERVED_MFR_3180 +{0x33E4, 0x0080}, // RESERVED_MFR_33E4 #if 1 {0x3004, AR0231_X_START}, // X_ADDR_START_ @@ -298,12 +300,8 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { //3exp Timing and Exposure {0x3082, 0x0008}, // OPERATION_MODE_CTRL {0x30BA, 0x11E2}, // DIGITAL_CTRL - -//Row and Pixel Timing -{0x300A, 0x5af}, -{0x300C, 0x7ba}, - -//Exposure Settings +{0x300A, 0x05AF}, // FRAME_LENGTH_LINES_ +{0x300C, 0x07BA}, // LINE_LENGTH_PCK_ {0x3042, 0x0000}, // EXTRA_DELAY {0x3238, 0x0222}, // EXPOSURE_RATIO {0x1008, 0x0374}, // FINE_INTEGRATION_TIME_MIN @@ -315,31 +313,29 @@ static const struct ar0231_reg ar0231_regs_wizard_rev4[] = { {0x321E, 0x06A6}, // FINE_INTEGRATION_TIME2 {0x3222, 0x06A6}, // FINE_INTEGRATION_TIME3 {0x30B0, 0x0B02}, // DIGITAL_TEST - {0x32EA, 0x3C0E}, // RESERVED_MFR_32EA {0x32EC, 0x72A1}, // RESERVED_MFR_32EC + //Parallel HDR 12 bit Output {0x31D0, 0x0001}, // COMPANDING +{0x31AE, 0x0001}, // SERIAL_FORMAT {0x31AC, 0x140C}, // DATA_FORMAT_BITS -//{0x301A, 0x01d8}, // RESET_REGISTER -{0x301A, 0x01dc}, // RESET_REGISTER - stream on - -//{AR0231_DELAY, 100}, // Wait 100ms - #if 0 // no need for front only camera /* Enable trigger input */ {0x340A, 0x00E0}, // GPIO_CONTROL1: GPIO1 is trigger {0x340C, 0x0002}, // GPIO_CONTROL2: GPIO1 is trigger {0x30CE, 0x0120}, // TRIGGER_MODE //{0x30DC, 0x0120}, // TRIGGER_DELAY +{0x301A, 0x01D8}, // GPI pins enable #endif -#define NEW_TIMINGS -#ifdef NEW_TIMINGS -/* the sequence must be updated to use following timings, now it is a hack */ +{0x301A, 0x01DC}, // RESET_REGISTER - stream on + +#if 1 {0x300A, AR0231_SENSOR_HEIGHT + 225}, // FRAME_LENGTH_LINES_ {0x300C, AR0231_SENSOR_WIDTH + 120}, // LINE_LENGTH_PCK_ +/* the sequence must be updated to use following timings, now it is a hack */ {0x1008, 0x0fff}, // FINE_INTEGRATION_TIME_MIN {0x100C, 0x0fff}, // FINE_INTEGRATION_TIME2_MIN {0x100E, 0x0fff}, // FINE_INTEGRATION_TIME3_MIN diff --git a/drivers/media/i2c/soc_camera/ar0231_rev6.h b/drivers/media/i2c/soc_camera/ar0231_rev6.h new file mode 100644 index 0000000..12e0ce5 --- /dev/null +++ b/drivers/media/i2c/soc_camera/ar0231_rev6.h @@ -0,0 +1,343 @@ +/* + * ON Semiconductor AR0231 sensor camera wizard 1920x1080@30/BGGR/MIPI + * + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* Parallel Timing Setup 27MHz In 88 MHz Out */ +static const struct ar0231_reg ar0231_regs_wizard_rev6_dvp[] = { +{0x301A, 0x0001}, // reset +{0x301A, 0x10D8}, // Stream off and setup parallel +{0x3070, 0x0000}, // 1: Solid color test pattern, + // 2: Full color bar test pattern, + // 3: Fade to grey color bar test pattern, + //256: Walking 1 test pattern (12 bit) +{0x3072, 0x0123}, // R +{0x3074, 0x0456}, // G(GR row) +{0x3076, 0x0abc}, // B +{0x3078, 0x0def}, // G(GB row) +#ifdef AR0231_DISPLAY_PATTERN_FIXED +{0x3070, 0x0001}, +#endif +#ifdef AR0231_DISPLAY_PATTERN_COLOR_BAR +{0x3070, 0x0002}, +#endif + +//Recommended Settings +{0x3056, 0x0080}, // GREEN1_GAIN +{0x305C, 0x0080}, // GREEN2_GAIN +{0x3058, 0x0080}, // BLUE_GAIN +{0x305A, 0x0080}, // RED_GAIN +{0x3138, 0x000B}, // OTPM_TCFG_OPT +{0x3372, 0xF54F}, // RESERVED_MFR_3372 +{0x337A, 0x0D70}, // RESERVED_MFR_337A +{0x337E, 0x1FFD}, // RESERVED_MFR_337E +{0x3382, 0x00C0}, // RESERVED_MFR_3382 +{0x3C04, 0x0E80}, // RESERVED_MFR_3C04 +{0x3F90, 0x06E1}, // RESERVED_MFR_3F90 +{0x3F92, 0x06E1}, // RESERVED_MFR_3F92 +{0x350E, 0x1F14}, // RESERVED_MFR_350E +{0x350E, 0xFF10}, // RESERVED_MFR_350E +{0x3506, 0x4444}, // RESERVED_MFR_3506 +{0x3508, 0x4444}, // RESERVED_MFR_3508 +{0x350A, 0x4465}, // RESERVED_MFR_350A +{0x350C, 0x055F}, // RESERVED_MFR_350C +{0x3566, 0x9D38}, // RESERVED_MFR_3566 +{0x3518, 0x1FFE}, // RESERVED_MFR_3518 +{0x3520, 0xC688}, // RESERVED_MFR_3520 +{0x3522, 0x88C0}, // RESERVED_MFR_3522 +{0x3524, 0xC0C6}, // RESERVED_MFR_3524 +{0x352C, 0xC6C6}, // RESERVED_MFR_352C +{0x3528, 0x0900}, // RESERVED_MFR_3528 +{0x3528, 0x9900}, // RESERVED_MFR_3528 +{0x3528, 0x9909}, // RESERVED_MFR_3528 +{0x3528, 0x9999}, // RESERVED_MFR_3528 +{0x352A, 0x089F}, // RESERVED_MFR_352A +{0x352E, 0x0001}, // RESERVED_MFR_352E +{0x352E, 0x0011}, // RESERVED_MFR_352E +{0x3530, 0x0400}, // RESERVED_MFR_3530 +{0x3530, 0x4400}, // RESERVED_MFR_3530 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF00}, // RESERVED_MFR_3536 +{0x3536, 0xFF02}, // RESERVED_MFR_3536 +{0x3536, 0xFF06}, // RESERVED_MFR_3536 +{0x3536, 0xFF06}, // RESERVED_MFR_3536 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x3538, 0xFFFF}, // RESERVED_MFR_3538 +{0x353A, 0x9000}, // RESERVED_MFR_353A +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x353C, 0x3F00}, // RESERVED_MFR_353C +{0x32EC, 0x72A1}, // RESERVED_MFR_32EC +{0x3540, 0xC637}, // RESERVED_MFR_3540 +{0x3540, 0xC637}, // RESERVED_MFR_3540 +{0x3540, 0xC637}, // RESERVED_MFR_3540 +{0x3542, 0x584B}, // RESERVED_MFR_3542 +{0x3542, 0x464B}, // RESERVED_MFR_3542 +{0x3544, 0x565A}, // RESERVED_MFR_3544 +{0x3544, 0x4B5A}, // RESERVED_MFR_3544 +{0x3546, 0x545A}, // RESERVED_MFR_3546 +{0x3546, 0x5A5A}, // RESERVED_MFR_3546 +{0x3548, 0x6400}, // RESERVED_MFR_3548 +{0x3556, 0x101F}, // RESERVED_MFR_3556 +{0x3566, 0x9D38}, // RESERVED_MFR_3566 +{0x3566, 0x1D38}, // RESERVED_MFR_3566 +{0x3566, 0x1D28}, // RESERVED_MFR_3566 +{0x3566, 0x1128}, // RESERVED_MFR_3566 +{0x3566, 0x1328}, // RESERVED_MFR_3566 +{0x3566, 0x3328}, // RESERVED_MFR_3566 +{0x3528, 0xDDDD}, // RESERVED_MFR_3528 + +//Sequencer Update +{0x2512, 0x8000}, // SEQ_CTRL_PORT +{0x2510, 0x0905}, // SEQ_DATA_PORT +{0x2510, 0x3350}, // SEQ_DATA_PORT +{0x2510, 0x2004}, // SEQ_DATA_PORT +{0x2510, 0x1460}, // SEQ_DATA_PORT +{0x2510, 0x1578}, // SEQ_DATA_PORT +{0x2510, 0x1360}, // SEQ_DATA_PORT +{0x2510, 0x7B24}, // SEQ_DATA_PORT +{0x2510, 0xFF24}, // SEQ_DATA_PORT +{0x2510, 0xFF24}, // SEQ_DATA_PORT +{0x2510, 0xEA24}, // SEQ_DATA_PORT +{0x2510, 0x1022}, // SEQ_DATA_PORT +{0x2510, 0x2410}, // SEQ_DATA_PORT +{0x2510, 0x155A}, // SEQ_DATA_PORT +{0x2510, 0x1342}, // SEQ_DATA_PORT +{0x2510, 0x1400}, // SEQ_DATA_PORT +{0x2510, 0x24FF}, // SEQ_DATA_PORT +{0x2510, 0x24FF}, // SEQ_DATA_PORT +{0x2510, 0x24EA}, // SEQ_DATA_PORT +{0x2510, 0x2324}, // SEQ_DATA_PORT +{0x2510, 0x647A}, // SEQ_DATA_PORT +{0x2510, 0x2404}, // SEQ_DATA_PORT +{0x2510, 0x052C}, // SEQ_DATA_PORT +{0x2510, 0x400A}, // SEQ_DATA_PORT +{0x2510, 0xFF0A}, // SEQ_DATA_PORT +{0x2510, 0xFF0A}, // SEQ_DATA_PORT +{0x2510, 0x1808}, // SEQ_DATA_PORT +{0x2510, 0x3851}, // SEQ_DATA_PORT +{0x2510, 0x1440}, // SEQ_DATA_PORT +{0x2510, 0x0004}, // SEQ_DATA_PORT +{0x2510, 0x0801}, // SEQ_DATA_PORT +{0x2510, 0x0408}, // SEQ_DATA_PORT +{0x2510, 0x1180}, // SEQ_DATA_PORT +{0x2510, 0x15DC}, // SEQ_DATA_PORT +{0x2510, 0x134C}, // SEQ_DATA_PORT +{0x2510, 0x1002}, // SEQ_DATA_PORT +{0x2510, 0x1016}, // SEQ_DATA_PORT +{0x2510, 0x1181}, // SEQ_DATA_PORT +{0x2510, 0x1189}, // SEQ_DATA_PORT +{0x2510, 0x1056}, // SEQ_DATA_PORT +{0x2510, 0x1210}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x0D08}, // SEQ_DATA_PORT +{0x2510, 0x0913}, // SEQ_DATA_PORT +{0x2510, 0x13C8}, // SEQ_DATA_PORT +{0x2510, 0x092B}, // SEQ_DATA_PORT +{0x2510, 0x1588}, // SEQ_DATA_PORT +{0x2510, 0x1388}, // SEQ_DATA_PORT +{0x2510, 0x090B}, // SEQ_DATA_PORT +{0x2510, 0x11D9}, // SEQ_DATA_PORT +{0x2510, 0x091D}, // SEQ_DATA_PORT +{0x2510, 0x1441}, // SEQ_DATA_PORT +{0x2510, 0x0903}, // SEQ_DATA_PORT +{0x2510, 0x1214}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x10D6}, // SEQ_DATA_PORT +{0x2510, 0x1210}, // SEQ_DATA_PORT +{0x2510, 0x1212}, // SEQ_DATA_PORT +{0x2510, 0x1210}, // SEQ_DATA_PORT +{0x2510, 0x11DD}, // SEQ_DATA_PORT +{0x2510, 0x11D9}, // SEQ_DATA_PORT +{0x2510, 0x1056}, // SEQ_DATA_PORT +{0x2510, 0x090B}, // SEQ_DATA_PORT +{0x2510, 0x11DB}, // SEQ_DATA_PORT +{0x2510, 0x0915}, // SEQ_DATA_PORT +{0x2510, 0x119B}, // SEQ_DATA_PORT +{0x2510, 0x090F}, // SEQ_DATA_PORT +{0x2510, 0x11BB}, // SEQ_DATA_PORT +{0x2510, 0x121A}, // SEQ_DATA_PORT +{0x2510, 0x1210}, // SEQ_DATA_PORT +{0x2510, 0x1460}, // SEQ_DATA_PORT +{0x2510, 0x1250}, // SEQ_DATA_PORT +{0x2510, 0x1076}, // SEQ_DATA_PORT +{0x2510, 0x10E6}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x15AB}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x13A8}, // SEQ_DATA_PORT +{0x2510, 0x1240}, // SEQ_DATA_PORT +{0x2510, 0x1260}, // SEQ_DATA_PORT +{0x2510, 0x0923}, // SEQ_DATA_PORT +{0x2510, 0x158D}, // SEQ_DATA_PORT +{0x2510, 0x138D}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x0B09}, // SEQ_DATA_PORT +{0x2510, 0x0108}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x1440}, // SEQ_DATA_PORT +{0x2510, 0x091D}, // SEQ_DATA_PORT +{0x2510, 0x1588}, // SEQ_DATA_PORT +{0x2510, 0x1388}, // SEQ_DATA_PORT +{0x2510, 0x092D}, // SEQ_DATA_PORT +{0x2510, 0x1066}, // SEQ_DATA_PORT +{0x2510, 0x0905}, // SEQ_DATA_PORT +{0x2510, 0x0C08}, // SEQ_DATA_PORT +{0x2510, 0x090B}, // SEQ_DATA_PORT +{0x2510, 0x1441}, // SEQ_DATA_PORT +{0x2510, 0x090D}, // SEQ_DATA_PORT +{0x2510, 0x10E6}, // SEQ_DATA_PORT +{0x2510, 0x0901}, // SEQ_DATA_PORT +{0x2510, 0x1262}, // SEQ_DATA_PORT +{0x2510, 0x1260}, // SEQ_DATA_PORT +{0x2510, 0x11BF}, // SEQ_DATA_PORT +{0x2510, 0x11BB}, // SEQ_DATA_PORT +{0x2510, 0x1066}, // SEQ_DATA_PORT +{0x2510, 0x11FB}, // SEQ_DATA_PORT +{0x2510, 0x0935}, // SEQ_DATA_PORT +{0x2510, 0x11BB}, // SEQ_DATA_PORT +{0x2510, 0x1263}, // SEQ_DATA_PORT +{0x2510, 0x1260}, // SEQ_DATA_PORT +{0x2510, 0x1400}, // SEQ_DATA_PORT +{0x2510, 0x1510}, // SEQ_DATA_PORT +{0x2510, 0x11B8}, // SEQ_DATA_PORT +{0x2510, 0x12A0}, // SEQ_DATA_PORT +{0x2510, 0x1200}, // SEQ_DATA_PORT +{0x2510, 0x1026}, // SEQ_DATA_PORT +{0x2510, 0x1000}, // SEQ_DATA_PORT +{0x2510, 0x1342}, // SEQ_DATA_PORT +{0x2510, 0x1100}, // SEQ_DATA_PORT +{0x2510, 0x7A06}, // SEQ_DATA_PORT +{0x2510, 0x0915}, // SEQ_DATA_PORT +{0x2510, 0x0507}, // SEQ_DATA_PORT +{0x2510, 0x0841}, // SEQ_DATA_PORT +{0x2510, 0x3750}, // SEQ_DATA_PORT +{0x2510, 0x2C2C}, // SEQ_DATA_PORT +{0x2510, 0xFE05}, // SEQ_DATA_PORT +{0x2510, 0xFE13}, // SEQ_DATA_PORT +{0x1008, 0x0361}, // FINE_INTEGRATION_TIME_MIN +{0x100C, 0x0589}, // FINE_INTEGRATION_TIME2_MIN +{0x100E, 0x07B1}, // FINE_INTEGRATION_TIME3_MIN +{0x1010, 0x0139}, // FINE_INTEGRATION_TIME4_MIN +{0x3230, 0x0304}, // FINE_CORRECTION +{0x3232, 0x052C}, // FINE_CORRECTION2 +{0x3234, 0x0754}, // FINE_CORRECTION3 +{0x3236, 0x00DC}, // FINE_CORRECTION4 +{0x3566, 0x3328}, // RESERVED_MFR_3566 +{0x350C, 0x055F}, // RESERVED_MFR_350C +{0x32D0, 0x3A02}, // RESERVED_MFR_32D0 +{0x32D2, 0x3508}, // RESERVED_MFR_32D2 +{0x32D4, 0x3702}, // RESERVED_MFR_32D4 +{0x32D6, 0x3C04}, // RESERVED_MFR_32D6 +{0x32DC, 0x370A}, // RESERVED_MFR_32DC + +//Parallel Timing Setup 27MHz In 88 MHz Out +{0x302A, 0x0009}, // VT_PIX_CLK_DIV +{0x302C, 0x0001}, // VT_SYS_CLK_DIV +{0x302E, 0x0003}, // PRE_PLL_CLK_DIV +{0x3030, 0x0058}, // PLL_MULTIPLIER +{0x3036, 0x0008}, // OP_WORD_CLK_DIV +{0x3038, 0x0001}, // OP_SYS_CLK_DIV +{0x30B0, 0x0B02}, // DIGITAL_TEST + +//Readout Mode Configuration +{0x30A2, 0x0001}, // X_ODD_INC_ +{0x30A6, 0x0001}, // Y_ODD_INC_ +{0x3040, 0x0000}, // READ_MODE +{0x3082, 0x0008}, // OPERATION_MODE_CTRL +{0x30BA, 0x11E2}, // DIGITAL_CTRL +{0x3044, 0x0400}, // DARK_CONTROL +#ifdef AR0231_EMBEDDED_LINE +{0x3064, 0x1982}, // SMIA_TEST +#else +{0x3064, 0x1802}, // SMIA_TEST +#endif +{0x33E0, 0x0880}, // RESERVED_MFR_33E0 +{0x3180, 0x0080}, // RESERVED_MFR_3180 +{0x33E4, 0x0080}, // RESERVED_MFR_33E4 +{0x33E0, 0x0C80}, // RESERVED_MFR_33E0 + +#if 1 +{0x3004, AR0231_X_START}, // X_ADDR_START_ +{0x3008, AR0231_X_END}, // X_ADDR_END_ +{0x3002, AR0231_Y_START}, // Y_ADDR_START_ +{0x3006, AR0231_Y_END}, // Y_ADDR_END_ +{0x3402, 0x0000 | AR0231_MAX_WIDTH}, // X_OUTPUT_CONTROL +{0x3404, 0x0000 | AR0231_MAX_HEIGHT}, // Y_OUTPUT_CONTROL +#else +{0x3004, 0}, // X_ADDR_START_ +{0x3008, 0x0787}, // X_ADDR_END_ +{0x3002, 0x0000}, // Y_ADDR_START_ +{0x3006, 0x04B7}, // Y_ADDR_END_ +{0x3402, 0x0788}, // RESERVED_MFR_3402 +{0x3402, 0x0F10}, // RESERVED_MFR_3402 +{0x3404, 0x0440}, // RESERVED_MFR_3404 +{0x3404, 0x0970}, // RESERVED_MFR_3404 +#endif +{0x3032, 0x0000}, // SCALING_MODE +{0x3400, 0x0010}, // RESERVED_MFR_3400 + +//3exp Timing and Exposure +{0x3082, 0x0008}, // OPERATION_MODE_CTRL +{0x30BA, 0x11E2}, // DIGITAL_CTRL +{0x300A, 0x05CA}, // FRAME_LENGTH_LINES_ +{0x300C, 0x07BA}, // LINE_LENGTH_PCK_ +{0x3042, 0x0000}, // EXTRA_DELAY +{0x3238, 0x0222}, // EXPOSURE_RATIO +{0x3012, 0x0163}, // COARSE_INTEGRATION_TIME_ +{0x3014, 0x08CC}, // FINE_INTEGRATION_TIME_ +{0x321E, 0x08CC}, // FINE_INTEGRATION_TIME2 +{0x3222, 0x0254}, // FINE_INTEGRATION_TIME3 +{0x30B0, 0x0A00}, // DIGITAL_TEST +{0x32EA, 0x3C0E}, // RESERVED_MFR_32EA +{0x32EC, 0x72A1}, // RESERVED_MFR_32EC + +//Parallel HDR 12 bit Output +{0x31D0, 0x0001}, // COMPANDING +{0x31AE, 0x0001}, // SERIAL_FORMAT +{0x31AC, 0x140C}, // DATA_FORMAT_BITS + +#if 0 // no need for front only camera +/* Enable trigger input */ +{0x340A, 0x00E0}, // GPIO_CONTROL1: GPIO1 is trigger +{0x340C, 0x0002}, // GPIO_CONTROL2: GPIO1 is trigger +{0x30CE, 0x0120}, // TRIGGER_MODE +//{0x30DC, 0x0120}, // TRIGGER_DELAY +{0x301A, 0x01D8}, // GPI pins enable +#endif + +{0x301A, 0x01DC}, // RESET_REGISTER - stream on + +#if 1 +{0x300A, AR0231_SENSOR_HEIGHT + 225}, // FRAME_LENGTH_LINES_ +{0x300C, AR0231_SENSOR_WIDTH + 120}, // LINE_LENGTH_PCK_ +/* the sequence must be updated to use following timings, now it is a hack */ +{0x1008, 0x0fff}, // FINE_INTEGRATION_TIME_MIN +{0x100C, 0x0fff}, // FINE_INTEGRATION_TIME2_MIN +{0x100E, 0x0fff}, // FINE_INTEGRATION_TIME3_MIN +{0x1010, 0x0fff}, // FINE_INTEGRATION_TIME4_MIN +#endif +}; diff --git a/drivers/media/i2c/soc_camera/ar0231_rev7.h b/drivers/media/i2c/soc_camera/ar0231_rev7.h index c05c3ea..885d34e 100644 --- a/drivers/media/i2c/soc_camera/ar0231_rev7.h +++ b/drivers/media/i2c/soc_camera/ar0231_rev7.h @@ -9,27 +9,6 @@ * option) any later version. */ -//#define AR0231_DISPLAY_PATTERN_FIXED -//#define AR0231_DISPLAY_PATTERN_COLOR_BAR - -#define AR0231_MAX_WIDTH 1920 -#define AR0231_MAX_HEIGHT 1200 - -#define AR0231_DELAY 0xffff - -#define AR0231_SENSOR_WIDTH 1928 -#define AR0231_SENSOR_HEIGHT 1208 - -#define AR0231_X_START ((AR0231_SENSOR_WIDTH - AR0231_MAX_WIDTH) / 2) -#define AR0231_Y_START ((AR0231_SENSOR_HEIGHT - AR0231_MAX_HEIGHT) / 2) -#define AR0231_X_END (AR0231_X_START + AR0231_MAX_WIDTH - 1) -#define AR0231_Y_END (AR0231_Y_START + AR0231_MAX_HEIGHT - 1) - -struct ar0231_reg { - u16 reg; - u16 val; -}; - /* 3Exp HDR Full Resolution Mode MIPI 4lane 12bit 30FPS, XCLK=27MHz */ static const struct ar0231_reg ar0231_regs_wizard_rev7[] = { {0x301A, 0x18}, // MIPI, stream OFF @@ -322,12 +301,14 @@ static const struct ar0231_reg ar0231_regs_wizard_rev7[] = { #endif /* Sensor Setup */ #if 1 /* Serial 12-bit Timing Setup */ -{0x302A, 6}, // vt_pix_clk_div -{0x302C, 1}, // vt_sys_clk_div +/* PCLK=27Mhz/PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 *2 */ +/* PCLK=27Mhz/2 *44/1/12 *2= 99Mhz - TI serializers */ +{0x302A, 6}, // vt_pix_clk_div (P2 divider) +{0x302C, 1}, // vt_sys_clk_div (P1 divider) {0x302E, 2}, // pre_pll_clk_div {0x3030, 44}, // pll_multiplier -{0x3036, 12}, // op_word_clk_div -{0x3038, 1}, // op_sys_clk_div +{0x3036, 12}, // op_word_clk_div (P4 divider) +{0x3038, 1}, // op_sys_clk_div (P3 divider) {0x30B0, 0x800}, // digital_test: pll_complete_bypass=0 #endif /* Serial 12-bit Timing Setup */ @@ -416,3 +397,49 @@ static const struct ar0231_reg ar0231_regs_wizard_rev7[] = { {0x301A, 0x0118}, // GPI pins enable #endif }; + +/* 3Exp HDR Full Resolution Mode Parallel 12bit 30FPS, XCLK=24MHz */ +static const struct ar0231_reg ar0231_regs_wizard_rev7_dvp[] = { +#if 1 /* Parallel Timing Setup */ +/* PCLK=24Mhz/PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 */ +/* PCLK=24Mhz/3 *88/1/8 = 88Mhz - TI serializers */ +{0x302A, 8}, // vt_pix_clk_div (P2 divider) +{0x302C, 1}, // vt_sys_clk_div (P1 divider) +{0x302E, 3}, // pre_pll_clk_div +{0x3030, 88}, // pll_multiplier +{0x3036, 8}, // op_word_clk_div (P4 divider) +{0x3038, 1}, // op_sys_clk_div (P3 divider) +{0x30B0, 0x800}, // digital_test: pll_complete_bypass=0 +#endif + +#if 1 /* 3exp Timing and Exposure - Parallel */ +{0x3082, 0x8}, // operation_mode_ctrl +{0x30BA, 0x11E2}, // digital_ctrl: num_exp_max=2 + +/* Row and Pixel Timing */ +#if 1 +{0x300A, AR0231_SENSOR_HEIGHT + 225}, // frame_length_lines_ +{0x300C, AR0231_SENSOR_WIDTH + 120}, // line_length_pck_ +#else +{0x300C, 1978}, // line_length_pck_ +{0x300A, 1482}, // frame_length_lines_ +#endif +{0x3042, 0}, // extra_delay + +/* Exposure Settings */ +//{0x3238, 0x222}, // exposure_ratio +//{0x3012, 355}, // coarse_integration_time_ +{0x3014, 2178}, // fine_integration_time_ +{0x321E, 2178}, // fine_integration_time2 +{0x3222, 2178}, // fine_integration_time3 +{0x30B0, 0x800}, // digital_test: set bit11 +{0x32EA, 0x3C0E}, +{0x32EC, 0x72A1}, +#endif /* 3exp Timing and Exposure - Parallel */ + +#if 1 /* Parallel HDR 12 bit Output */ +{0x31AE, 0x001}, // serial_format: +#endif + +{0x301A, 0x01d8}, // RESET_REGISTER parallel pins enable +}; -- 2.7.4