From 31f98f9d7765dca4405ccf7b982d094bcd56e9d3 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 6 May 2019 22:51:09 +0300 Subject: [PATCH 111/122] lvds: AR0233: migrate to composed tables Migrate to composed table Add seperate EXTCLK (coming not from CLKOUT) --- drivers/media/i2c/soc_camera/ar0233.c | 49 +++++++--- drivers/media/i2c/soc_camera/ar0233_rev1.h | 104 ++++++++++++-------- drivers/media/i2c/soc_camera/ar0233_rev2.h | 147 ++++++++++++++--------------- 3 files changed, 171 insertions(+), 129 deletions(-) diff --git a/drivers/media/i2c/soc_camera/ar0233.c b/drivers/media/i2c/soc_camera/ar0233.c index 8257cf1..54cc38a 100644 --- a/drivers/media/i2c/soc_camera/ar0233.c +++ b/drivers/media/i2c/soc_camera/ar0233.c @@ -48,23 +48,42 @@ static int trigger = 0; module_param(trigger, int, 0644); MODULE_PARM_DESC(trigger, " Trigger gpio number (default: 0 - GPIO0) "); +static int extclk = 23; +module_param(extclk, int, 0644); +MODULE_PARM_DESC(extclk, " EXTCLK value in MHz (default: 23) "); + +static char *mode = "hdr"; +module_param(mode, charp, 0644); +MODULE_PARM_DESC(mode, " Modes linear,hdr,seplus (default: hdr)"); + static inline struct ar0233_priv *to_ar0233(const struct i2c_client *client) { return container_of(i2c_get_clientdata(client), struct ar0233_priv, sd); } -static int ar0233_set_regs(struct i2c_client *client, - const struct ar0233_reg *regs, int nr_regs) +static int ar0233_set_regs(struct i2c_client *client, const struct ar0233_reg **pregs) { - int i; + struct ar0233_priv *priv = to_ar0233(client); + const struct ar0233_reg *regs; + int i, j; - for (i = 0; i < nr_regs; i++) { - if (regs[i].reg == AR0233_DELAY) { - mdelay(regs[i].val); - continue; - } + for (j = 0; ; j++) { + regs = pregs[j]; - reg16_write16(client, regs[i].reg, regs[i].val); + if (!pregs[j]) + break; + + for (i = 0; ; i++) { + if (!regs[i].reg && !regs[i].val) + break; + + if (regs[i].reg == AR0233_DELAY) { + mdelay(regs[i].val); + continue; + } + + reg16_write16(client, regs[i].reg, regs[i].val); + } } return 0; @@ -415,16 +434,22 @@ static int ar0233_initialize(struct i2c_client *client) /* Program wizard registers */ switch (rev & 0xf) { case 0x1: - ar0233_set_regs(client, ar0233_regs_wizard_rev1, ARRAY_SIZE(ar0233_regs_wizard_rev1)); + ar0233_set_regs(client, ar0233_regs_hdr_mipi_12bit_30fps_rev1); break; case 0x2: - ar0233_set_regs(client, ar0233_regs_wizard_rev2, ARRAY_SIZE(ar0233_regs_wizard_rev2)); + if (extclk == 27) + ar0233_regs_hdr_mipi_12bit_30fps_rev2[4] = ar0233_rev2_pll_27_102_4lane_12b; + + if (strcmp(mode, "hdr") == 0) + ar0233_set_regs(client, ar0233_regs_hdr_mipi_12bit_30fps_rev2); + else + dev_err(&client->dev, "Unsupported mode %s\n", mode); break; default: dev_err(&client->dev, "Unsupported chip revision\n"); } - /* Enable trigger*/ + /* Enable trigger */ reg16_write16(client, 0x340A, (~(BIT(priv->trigger) << 4)) & 0xf0); /* GPIO_CONTROL1: GPIOn input enable */ reg16_write16(client, 0x340C, (0x2 << 2*priv->trigger)); /* GPIO_CONTROL2: GPIOn is trigger */ reg16_write16(client, 0x30CE, 0x0120); /* TRIGGER_MODE */ diff --git a/drivers/media/i2c/soc_camera/ar0233_rev1.h b/drivers/media/i2c/soc_camera/ar0233_rev1.h index 288b465..7b6370b 100644 --- a/drivers/media/i2c/soc_camera/ar0233_rev1.h +++ b/drivers/media/i2c/soc_camera/ar0233_rev1.h @@ -9,11 +9,9 @@ * option) any later version. */ -/* 3Exp HDR 1080p Mode MIPI-4lane 12-bit 30FPS, XCLK=24MHz */ -static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { -{0x301A, 0x18}, // MIPI, stream OFF -{AR0233_DELAY, 200}, // Wait 200ms - +static const struct ar0233_reg ar0233_rev1_Reset[] = { +{0x301A, 0x0018}, // Stream off and setup MIPI +{AR0233_DELAY, 200}, {0x3070, 0x0000}, // 1: Solid color test pattern, // 2: Full color bar test pattern, // 3: Fade to grey color bar test pattern, @@ -28,10 +26,12 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { #ifdef AR0233_DISPLAY_PATTERN_COLOR_BAR {0x3070, 0x0002}, #endif -{AR0233_DELAY, 100}, // Wait 100ms +{AR0233_DELAY, 100}, +{ } +}; /* Reset */ -#if 1 /* Sequencer Settings */ -#if 1 /* Design_recommended_settings_v5 */ +static const struct ar0233_reg ar0233_rev1_Sequencer_Settings[] = { +/* Design_recommended_settings_v5 */ {0x356C, 0xEA55}, //mte.Sensor.Register("DAC_LD_108_109").Value = 0xEA55& -- ADC write Memory delay 7 {0x3566, 0x2407}, //mte.Sensor.Register("DAC_LD_102_103").Value = 0x2407& -- Enable column amp bypass for 1x {0x3562, 0x1C08}, //mte.Sensor.Register("DAC_LD_98_99").Value = 0x1C08& -- Increase column amp current @@ -51,9 +51,9 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x353C, 0x9A0A}, //Boost_ref_Vaa lfm_dcghi(1) {0x3526, 0x9000}, //DWellhi(16) {0x352E, 0x90D}, //Dlfm_Dcghi(13),(Dlfm_Txhi_Buffer) = 9 -#endif /* Design_recommended_settings_v5 */ +/* Design_recommended_settings_v5 */ -#if 1 /* Pixel_char_recommended_settings_v2 */ +/* Pixel_char_recommended_settings_v2 */ //TXLO @HCG {0x3514, 0x555B}, //-0.85V {0x3578, 0x555B}, //-0.85V @@ -68,9 +68,9 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x3528, 0xEB0D}, //Ddcghi(13), txhi(11) //DRSTHI, DRSHI {0x352A, 0xA27}, //Drsthi (10), Drshi(7) -#endif /* Pixel_char_recommended_settings_v2 */ +/* Pixel_char_recommended_settings_v2 */ -#if 1 /* AR0233_Sequencer_LFM_HDR_v6 */ +/* Sequencer_LFM_HDR_v6 */ {0x2512, 0x8000}, {0x2510, 0x070f}, {0x2510, 0x1011}, @@ -1096,17 +1096,29 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x2510, 0xffff}, {0x2510, 0xffff}, {AR0233_DELAY, 100}, -#endif /* AR0233_Sequencer_LFM_HDR_v6 */ -#endif /* Sequencer Settings */ +/* Sequencer_LFM_HDR_v6 */ +{ } +}; /* Sequencer_Settings */ + +static const struct ar0233_reg ar0233_rev1_HDR_3exp_12bit[] = { +{0x3082, 0x8}, //num_exp = 3 +{0x3110, 0x11}, //Set bypass pix comb for HDR,Pre_hdr_gain_enable_07Jul +{0x30BA, 0x1122}, //num_exp_max =3 +{0x31AC, 0x140C}, //12 bit output +{0x31D0, 0x1}, // Companding -{0x3082, 0x8}, //0x3082 = 2, 3 exposures -{0x3110, 0x11}, //Set bypass pix comb for HDR,Pre_hdr_gain_enable_07Jul -{0x30BA, 0x1122}, //Num_exp_max +{0x3044, 0x0400}, //Dark_control + +// FPS = 103.5MHz / reg0x300A / reg0x300C +{0x300A, AR0233_SENSOR_HEIGHT + 100}, // Frame_length_Lines +{0x300C, AR0233_SENSOR_WIDTH + 400}, // Line_length_pck {0x3012, 0x144}, //Integration_time +{ } +}; /* HDR_3exp_12bit */ -#if 1 /* Serial 12-bit Timing Setup_108Mhz */ -/* PCLK=24Mhz/PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 */ -/* PCLK=24Mhz/2 *54/1/6= 108Mhz - TI serializers */ +static const struct ar0233_reg ar0233_rev1_Serial_12bit_Timing_Setup_103p5[] = { +/* PCLK=DES_REFCLK /PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 */ +/* PCLK=23MHz/2 *54/1/6= 103.5Mhz - TI serializers */ {0x3030, 54}, //PLL_MULTIPLIER ; 0x3030 [11:0] {0x302E, 2}, //PRE_PLL_CLK_DIV ; 0x302E [5:0] {0x302C, 1}, //P1 divider (vt_sys_clk_div) @@ -1114,9 +1126,10 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x3038, 2}, //P3 divider (op_sys_clk_div); 0x3038 [4:0] {0x3036, 6}, //P4 divider (op_word_clk_div); 0x3036 [4:0] {0x31DC, 0x1FB0}, -#endif /* Serial 12-bit Timing Setup_108Mhz */ +{ } +}; /* Serial_12bit_Timing_Setup_103p5 */ -#if 1 /* MIPI 4 Lane 12BITS 30FPS_ext24_LIM */ +static const struct ar0233_reg ar0233_rev1_MIPI_4Lane_12BITS[] = { {0x31AE, 0x204}, //MIPI enable, 4 lanes {0x31B0, 0x4B}, //frame_preamble {0x31B2, 0x33}, //line_preamble @@ -1125,46 +1138,43 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x31B8, 0x4047}, //mipi_timing_2 {0x31BA, 0x105}, //mipi_timing_3 {0x31BC, 0x704}, //mipi_timing_4 -#endif /* MIPI 4 Lane 12BITS 30FPS_ext24_LIM */ - -#if 1 /* MIPI_DT_bit12 */ {0x3342, 0x122C}, // MIPI_F1_PDT_EDT {0x3346, 0x122C}, // MIPI_F2_PDT_EDT {0x334A, 0x122C}, // MIPI_F3_PDT_EDT {0x334E, 0x122C}, // MIPI_F4_PDT_EDT -#endif /* MIPI_DT_bit12 */ +{ } +}; /* MIPI_4Lane_12BITS */ -/* resolution */ +static const struct ar0233_reg ar0233_rev1_Full_resolution[] = { {0x3004, AR0233_X_START}, // X_ADDR_START_ {0x3008, AR0233_X_END}, // X_ADDR_END_ {0x3002, AR0233_Y_START}, // Y_ADDR_START_ {0x3006, AR0233_Y_END}, // Y_ADDR_END_ +{0x3402, (0x8000 & 0) | AR0233_MAX_WIDTH}, // X_OUTPUT_CONTROL +{0x3404, (0x8000 & 0) | AR0233_MAX_HEIGHT}, // Y_OUTPUT_CONTROL +{ } +}; /* Full_resolution */ +static const struct ar0233_reg ar0233_rev1_disable_embed_data_stat[] = { #ifdef AR0233_EMBEDDED_LINE {0x3040, 0x0000}, //Embedded stat2 and data2 rows {0x3064, 0x0180}, //Enable embedded data and stat #else {0x3064, 0x0}, //Disable embedded data and stat #endif +{ } +}; /* disable_embed_data_stat */ -// FPS = 108MHz / reg0x300A / reg0x300C * (DES_REF_XTAL/24MHz) -{0x300A, AR0233_SENSOR_HEIGHT + 100}, // Frame_length_Lines -{0x300C, AR0233_SENSOR_WIDTH + 400}, // Line_length_pck -//{0x300C, 0x960}, //Line_lenth_pck_FRN AEF -//{0x300A, 0x5DC}, //FLL - -#if 1 /* Gain_3.28x */ +static const struct ar0233_reg ar0233_rev1_Gain_3p28x[] = { {0x3022, 0x01}, // GROUPED_PARAMETER_HOLD_ {0x3362, 0x000F}, // DC_GAIN {0x3366, 0x1111}, {0x336A, 0x0000}, {0x3022, 0x00}, // GROUPED_PARAMETER_HOLD_ -#endif /* Gain_3.28x */ +{ } +}; /* Gain_3.28x */ -{0x31D0, 0x1}, // Companding -{0x31AC, 0x140C}, // DLO20 to 12output - -#if 1 /* MEC DLO default */ +static const struct ar0233_reg ar0233_rev1_MEC_DLO_default[] = { {0x3D00, 0x6F73}, // control {0x3D02, 0x0033}, {0x3364, 0x068C}, // dcg_trim = 13.1 @@ -1246,5 +1256,19 @@ static const struct ar0233_reg ar0233_regs_wizard_rev1[] = { {0x3D12, 0x0798}, {0x3D14, 0x001E}, {0x3D16, 0x045E}, -#endif /* MEC DLO default */ +{ } +}; /* MEC_DLO_default */ + +/* 3Exp HDR, 1280P, MIPI 4-lane 12-bit, 30fps, EXTCLK=23MHz (comes from deser) */ +static const struct ar0233_reg *ar0233_regs_hdr_mipi_12bit_30fps_rev1[] = { + ar0233_rev1_Reset, + ar0233_rev1_Sequencer_Settings, + ar0233_rev1_disable_embed_data_stat, + ar0233_rev1_HDR_3exp_12bit, + ar0233_rev1_Serial_12bit_Timing_Setup_103p5, + ar0233_rev1_MIPI_4Lane_12BITS, + ar0233_rev1_Full_resolution, + ar0233_rev1_Gain_3p28x, + ar0233_rev1_MEC_DLO_default, + NULL, }; diff --git a/drivers/media/i2c/soc_camera/ar0233_rev2.h b/drivers/media/i2c/soc_camera/ar0233_rev2.h index 0dea2dd..c821d35 100644 --- a/drivers/media/i2c/soc_camera/ar0233_rev2.h +++ b/drivers/media/i2c/soc_camera/ar0233_rev2.h @@ -1,7 +1,7 @@ /* * ON Semiconductor AR0233 sensor camera wizard 2048x1280@30/BGGR/MIPI * - * Copyright (C) 2018 Cogent Embedded, Inc. + * Copyright (C) 2018-2019 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,31 +9,9 @@ * option) any later version. */ -#define O1_Recommended_Defaults_LFM_HDR -#ifdef O1_Recommended_Defaults_LFM_HDR - #define Design_recommended_settings_REV2_V9 - #define Sequence_hidy_ar0233_REV2_V13 - #define Pre_hdr_gain_enable - #define Tempsensor_init -#endif -#define disable_embed_data_stat -#define HDR_3exp_12bit -#if 0 - #define pll_27_108_4lane_12b - #define mipi_108_12bit_4lane -#else - #define pll_27_124p5_4lane_12b - #define mipi_124p5_12bit_4lane -#endif -#define MIPI_DT_bit12 -#define LUT_24_to_12 -#define HDR_ratio_gain_default - -/* 3Exp HDR 1280P Mipi_12bit_4lane_30fps, XCLK=27MHz */ -static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { -{0x301A, 0x18}, // MIPI, stream OFF -{AR0233_DELAY, 200}, // Wait 200ms - +static const struct ar0233_reg ar0233_rev2_Reset[] = { +{0x301A, 0x0018}, // Stream off and setup MIPI +{AR0233_DELAY, 200}, {0x3070, 0x0000}, // 1: Solid color test pattern, // 2: Full color bar test pattern, // 3: Fade to grey color bar test pattern, @@ -48,10 +26,12 @@ static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { #ifdef AR0233_DISPLAY_PATTERN_COLOR_BAR {0x3070, 0x0002}, #endif -{AR0233_DELAY, 100}, // Wait 100ms +{AR0233_DELAY, 100}, +{ } +}; /* Reset */ -#ifdef O1_Recommended_Defaults_LFM_HDR -#ifdef Design_recommended_settings_REV2_V9 +static const struct ar0233_reg ar0233_rev2_O1_Recommended_Defaults_LFM_HDR[] = { +/* Design_recommended_settings_REV2_V9 */ {0x3C72, 0x0076}, {0x3C74, 0x0031}, {0x3C76, 0x00DC}, @@ -99,9 +79,9 @@ static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { {0x352A, 0x0827}, {0x352C, 0xA800}, {0x352E, 0x0908}, -#endif /* Design_recommended_settings_REV2_V9 */ +/* Design_recommended_settings_REV2_V9 */ -#ifdef Sequence_hidy_ar0233_REV2_V13 +/* Sequence_hidy_ar0233_REV2_V13 */ {0x2512, 0x8000}, {0x2510, 0x070f}, {0x2510, 0x1011}, @@ -1127,71 +1107,74 @@ static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { {0x2510, 0x3426}, {0x2510, 0x3614}, {AR0233_DELAY, 100}, -#endif /* Sequence_hidy_ar0233_REV2_V13 */ +/* Sequence_hidy_ar0233_REV2_V13 */ -#ifdef Pre_hdr_gain_enable +/* Pre_hdr_gain_enable */ {0x3110, 0x0011}, -#endif /* Pre_hdr_gain_enable */ -#ifdef Tempsensor_init +/* Tempsensor_init */ {0x3E94, 0x3007}, {0x3E6E, 0xE200}, {0x3E98, 0x1000}, {0x3F92, 0x4C00}, {0x30B8, 0x000B}, {0x30B8, 0x0003}, -#endif /* Tempsensor_init */ {0x3364, 0x0766}, //14.8 -#endif /* O1_Recommended_Defaults_LFM_HDR */ +{ } +}; /* O1_Recommended_Defaults_LFM_HDR */ -#ifdef disable_embed_data_stat +static const struct ar0233_reg ar0233_rev2_disable_embed_data_stat[] = { {0x3064, 0x0}, // Disable embedded data and stat -#endif /* disable_embed_data_stat */ +#ifdef AR0233_EMBEDDED_LINE +{0x3064, 0x0180}, // SMIA_TEST: enable emb data and stats +#endif +{ } +}; /* disable_embed_data_stat */ -#ifdef HDR_3exp_12bit +static const struct ar0233_reg ar0233_rev2_HDR_3exp_12bit[] = { {0x3082, 0x8}, //num_exp = 3 {0x30BA, 0x1122}, //num_exp_max =3 {0x31AC, 0x140C}, //12 bit output -#endif /* HDR_3exp_12bit */ -#ifdef pll_27_124p5_4lane_12b +{0x3044, 0x0400}, //Dark_control + +// FPS = 102MHz / reg0x300A / reg0x300C +{0x300A, AR0233_SENSOR_HEIGHT + 100}, // Frame_length_Lines +{0x300C, AR0233_SENSOR_WIDTH + 400}, // Line_length_pck +{0x3012, 0x144}, //Integration_time +{ } +}; /* HDR_3exp_12bit */ + +static const struct ar0233_reg ar0233_rev2_pll_23_102_4lane_12b[] = { // serial_data_rate was *2 in REV1. but not in REV2 -{0x3030, 0x53}, //PLL_MULTIPLIER +/* PCLK=DES_REFCLK/PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 */ +/* PCLK=23Mhz/0x3 *0x50/1/6= 102Mhz - TI serializers */ +{0x3030, 0x50}, //PLL_MULTIPLIER {0x302E, 0x3}, //PRE_PLL_CLK_DIV {0x302C, 0x701}, //P1 divider (vt_sys_clk_div) {0x302A, 0x6}, //P2 divider (vt_pix_clk_div) {0x3038, 0x2}, //P3 divider (op_sys_clk_div) {0x3036, 0x6}, //P4 divider (op_word_clk_div) {0x31DC, 0x1FB0}, //vcodiv -#endif /* pll_27_124p5_4lane_12b */ - -#ifdef mipi_124p5_12bit_4lane -{0x31AE, 0x204}, //serial type and lane -{0x31B0, 0x67}, //frame_preamble -{0x31B2, 0x30}, //line_preamble -{0x31B4, 0x22CC}, //mipi_timing_0 -{0x31B6, 0x33D3}, //mipi_timing_1 -{0x31B8, 0xB04D}, //mipi_timing_2 -{0x31BA, 0x411}, //mipi_timing_3 -{0x31BC, 0x940E}, //mipi_timing_4 -#endif /* mipi_124p5_12bit_4lane */ +{ } +}; /* pll_23_102_4lane_12b */ -#ifdef pll_27_108_4lane_12b +static const struct ar0233_reg ar0233_rev2_pll_27_102_4lane_12b[] = { // serial_data_rate was *2 in REV1. but not in REV2 -/* PCLK=27Mhz/PRE_PLL_CLK_DIV *PLL_MULTIPLIER /P1 /P4 */ -/* PCLK=27Mhz/0x3 *0x48/1/6= 108Mhz - TI serializers */ -{0x3030, 0x48}, //PLL_MULTIPLIER +/* PCLK=27Mhz/0x3 *0x44/1/6= 102Mhz - TI serializers */ +{0x3030, 0x44}, //PLL_MULTIPLIER {0x302E, 0x3}, //PRE_PLL_CLK_DIV {0x302C, 0x701}, //P1 divider (vt_sys_clk_div) {0x302A, 0x6}, //P2 divider (vt_pix_clk_div) {0x3038, 0x2}, //P3 divider (op_sys_clk_div) {0x3036, 0x6}, //P4 divider (op_word_clk_div) {0x31DC, 0x1FB0}, //vcodiv -#endif /* pll_27_108_4lane_12b */ +{ } +}; /* pll_27_102_4lane_12b */ -#ifdef mipi_108_12bit_4lane -{0x31AE, 0x204}, //MIPI_enable +static const struct ar0233_reg ar0233_rev2_mipi_12bit_4lane[] = { +{0x31AE, 0x204}, //serial type and lane {0x31B0, 0x67}, //frame_preamble {0x31B2, 0x30}, //line_preamble {0x31B4, 0x22CC}, //mipi_timing_0 @@ -1199,16 +1182,14 @@ static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { {0x31B8, 0xB04D}, //mipi_timing_2 {0x31BA, 0x411}, //mipi_timing_3 {0x31BC, 0x940E}, //mipi_timing_4 -#endif /* mipi_108_12bit_4lane */ - -#ifdef MIPI_DT_bit12 {0x3342, 0x122C}, // MIPI_F1_PDT_EDT {0x3346, 0x122C}, // MIPI_F2_PDT_EDT {0x334A, 0x122C}, // MIPI_F3_PDT_EDT {0x334E, 0x122C}, // MIPI_F4_PDT_EDT -#endif /* MIPI_DT_bit12 */ +{ } +}; /* mipi_12bit_4lane */ -#ifdef LUT_24_to_12 +static const struct ar0233_reg ar0233_rev2_LUT_24_to_12[] = { {0x31AC, 0x180C}, {0x31D0, 0x01}, //companding {0x33DA, 0}, @@ -1228,24 +1209,36 @@ static const struct ar0233_reg ar0233_regs_wizard_rev2[] = { {0x33F6, 0xFF70}, {0x33F8, 0xFF70}, {0x33FA, 0xFF70}, //LUT_15 -#endif /* LUT_24_to_12 */ +{ } +}; /* LUT_24_to_12 */ -/* resolution */ +static const struct ar0233_reg ar0233_rev2_Full_resolution[] = { {0x3004, AR0233_X_START}, // X_ADDR_START_ {0x3008, AR0233_X_END}, // X_ADDR_END_ {0x3002, AR0233_Y_START}, // Y_ADDR_START_ {0x3006, AR0233_Y_END}, // Y_ADDR_END_ +{0x3402, (0x8000 & 0) | AR0233_MAX_WIDTH}, // X_OUTPUT_CONTROL +{0x3404, (0x8000 & 0) | AR0233_MAX_HEIGHT}, // Y_OUTPUT_CONTROL +{ } +}; /* Full_resolution */ -{0x3044, 0x0400}, //Dark_control - -#ifdef HDR_ratio_gain_default +static const struct ar0233_reg ar0233_rev2_HDR_ratio_gain_default[] = { {0x3362, 0x000F}, //HCG {0x3366, 0x1111}, //1x {0x3238, 0x0444}, // Ratio 16x, Use retio setting -#endif /* HDR_ratio_gain_default */ +{ } +}; /* HDR_ratio_gain_default */ -// FPS = 124.5MHz / reg0x300A / reg0x300C * (DES_REF_XTAL/27MHz) -{0x300A, AR0233_SENSOR_HEIGHT + 100}, // Frame_length_Lines -{0x300C, AR0233_SENSOR_WIDTH + 400}, // Line_length_pck -{0x3012, 0x144}, //Integration_time +/* 3Exp HDR, 1280P, MIPI 4-lane 12-bit, 30fps, EXTCLK=23MHz (comes from deser) */ +static const struct ar0233_reg *ar0233_regs_hdr_mipi_12bit_30fps_rev2[] = { + ar0233_rev2_Reset, + ar0233_rev2_O1_Recommended_Defaults_LFM_HDR, + ar0233_rev2_disable_embed_data_stat, + ar0233_rev2_HDR_3exp_12bit, + ar0233_rev2_pll_23_102_4lane_12b, + ar0233_rev2_mipi_12bit_4lane, + ar0233_rev2_LUT_24_to_12, + ar0233_rev2_Full_resolution, + ar0233_rev2_HDR_ratio_gain_default, + NULL, }; -- 2.7.4