=====================
AM6 Clock Identifiers
=====================

.. _soc_doc_am65x_sr2_public_clks_desc_intro:


Clock for AM6 Device
====================

This chapter provides information on clock IDs that identify clocks
incoming and outgoing from devices identified via
:ref:`device IDs <soc_doc_am6_public_devices_desc_device_list>`
in AM6 SoC.


TISCI message Power Management APIs define a device ID and clock ID as
parameters allowing a user to specify granular control of clocks
for a particular SoC subsystem.

.. _soc_doc_am65x_sr2_public_clks_dev_list:


Device wise clock ID list for AM6 SoC
=====================================

This is an enumerated list of clocks per device ID that can be
controlled via the power management clock APIs

The following table describes functions implemented by clocks

+----------------------------------+---------------------------------------------------------------------------------------------+
| Function                         | Description                                                                                 |
+==================================+=============================================================================================+
| Input clock                      | Clock input to the SoC subsystem                                                            |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Output clock                     | Clock output from the SoC subsystem                                                         |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Input muxed clock                | Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Parent input clock option to XYZ | One of the parent clocks that can be used as a source clock to a input muxed clock          |
+----------------------------------+---------------------------------------------------------------------------------------------+

Also note: There are devices which do not have clock information.
These do have chapters in this document associated with them, however, these would be marked as:

**This device has no defined clocks.**

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

.. _soc_doc_am65x_sr2_public_clks_board0:


Clocks for BOARD0 Device
------------------------

Device: :ref:`AM6_DEV_BOARD0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 157)


.. note::


   BOARD0 is a special device that represents the board on which
   the SoC is mounted.

   Clocks that are incoming to or outgoing from the SoC are
   represented in this section from the *perspective of the board*.

   Function documented here implies:

   +----------------+---------------------------------------------------------------------------------------------+
   |    Function    | Description                                                                                 |
   +================+=============================================================================================+
   |  Input clock   | Clock is supplied from SoC to the board (It is an output of the SoC)                        |
   +----------------+---------------------------------------------------------------------------------------------+
   |  Output clock  | Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC) |
   +----------------+---------------------------------------------------------------------------------------------+

   **NOTE: Clocks which can be bi-directional are listed as Output clock**

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                               | Function                                                  |
+============+====================================================================================+===========================================================+
|          5 | DEV_BOARD0_BUS_MCU_OSPI1CLK_IN                                                     | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_BOARD0_BUS_REFCLK1P_IN                                                         | Input muxed clock                                         |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK        | Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN                                                  | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_BOARD0_BUS_MCU_OBSCLK_IN                                                       | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK         | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0    | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK         | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK  | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0   | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         36 | DEV_BOARD0_BUS_OBSCLK_IN                                                           | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         37 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                             | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         38 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK            | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         39 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK          | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         40 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK                | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         41 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                        | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         42 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK          | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         43 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK                | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         44 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK                  | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         45 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK                | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         46 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK             | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         47 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK   | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         48 | DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK                  | Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN     |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         54 | DEV_BOARD0_BUS_MCU_OSPI0CLK_IN                                                     | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         55 | DEV_BOARD0_BUS_DSS0PCLK_IN                                                         | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         58 | DEV_BOARD0_BUS_REFCLK0P_IN                                                         | Input muxed clock                                         |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         59 | DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         60 | DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         61 | DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK        | Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         62 | DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN   |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         68 | DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN                                                  | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         69 | DEV_BOARD0_BUS_MCU_CLKOUT_IN                                                       | Input muxed clock                                         |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         70 | DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5        | Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         71 | DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10       | Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         73 | DEV_BOARD0_BUS_SYSCLKOUT_IN                                                        | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         74 | DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN                                                    | Input clock                                               |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         75 | DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         76 | DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         77 | DEV_BOARD0_BUS_GPMCCLK_OUT                                                         | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         78 | DEV_BOARD0_BUS_MCASP2AHCLKX_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         79 | DEV_BOARD0_BUS_MCASP2AHCLKR_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         80 | DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         81 | DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         82 | DEV_BOARD0_BUS_MCASP0ACLKR_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         83 | DEV_BOARD0_BUS_MCASP0ACLKX_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         84 | DEV_BOARD0_BUS_EXT_REFCLK1_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         85 | DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         86 | DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         88 | DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT                                                   | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         89 | DEV_BOARD0_BUS_SPI1CLK_OUT                                                         | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         90 | DEV_BOARD0_BUS_MCASP2ACLKR_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         91 | DEV_BOARD0_BUS_MCASP1ACLKX_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         92 | DEV_BOARD0_BUS_MCASP1ACLKR_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         93 | DEV_BOARD0_BUS_MCASP2ACLKX_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         94 | DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         95 | DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         96 | DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT                                                 | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         97 | DEV_BOARD0_BUS_MCU_SPI0CLK_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         98 | DEV_BOARD0_BUS_MCU_SPI1CLK_OUT                                                     | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|         99 | DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        100 | DEV_BOARD0_BUS_SPI2CLK_OUT                                                         | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        101 | DEV_BOARD0_BUS_WKUP_TCK_OUT                                                        | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        102 | DEV_BOARD0_BUS_SPI3CLK_OUT                                                         | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        104 | DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT                                                 | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        105 | DEV_BOARD0_BUS_MCASP0AHCLKR_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        106 | DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT                                                 | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        107 | DEV_BOARD0_BUS_MCASP0AHCLKX_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        108 | DEV_BOARD0_BUS_CCDC0_PCLK_OUT                                                      | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        109 | DEV_BOARD0_HFOSC1_CLK_OUT                                                          | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        110 | DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        111 | DEV_BOARD0_BUS_MCASP1AHCLKX_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        113 | DEV_BOARD0_BUS_MCASP1AHCLKR_OUT                                                    | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        115 | DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        116 | DEV_BOARD0_BUS_SPI0CLK_OUT                                                         | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        119 | DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        120 | DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        121 | DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        122 | DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        123 | DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+
|        124 | DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT                                                | Output clock                                              |
+------------+------------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_cal0:


Clocks for CAL0 Device
----------------------

Device: :ref:`AM6_DEV_CAL0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 2)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_CAL0_BUS_CLK      | Input clock |
+------------+-----------------------+-------------+
|          1 | DEV_CAL0_BUS_CP_C_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cbass0:


Clocks for CBASS0 Device
------------------------

Device: :ref:`AM6_DEV_CBASS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 82)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK | Input clock |
+------------+-----------------------------------+-------------+
|          1 | DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cbass_debug0:


Clocks for CBASS_DEBUG0 Device
------------------------------

Device: :ref:`AM6_DEV_CBASS_DEBUG0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 83)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cbass_fw0:


Clocks for CBASS_FW0 Device
---------------------------

Device: :ref:`AM6_DEV_CBASS_FW0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 84)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------+-------------+
|   Clock ID | Name                                 | Function    |
+============+======================================+=============+
|          0 | DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK | Input clock |
+------------+--------------------------------------+-------------+
|          1 | DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK | Input clock |
+------------+--------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cbass_infra0:


Clocks for CBASS_INFRA0 Device
------------------------------

Device: :ref:`AM6_DEV_CBASS_INFRA0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 85)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|   Clock ID | Name                                                                                         | Function                                                          |
+============+==============================================================================================+===================================================================+
|          0 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK                                                         | Input muxed clock                                                 |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          1 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          2 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          3 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                 | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          4 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          5 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          6 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          7 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                 | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          8 | DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK                 | Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|          9 | DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK                                                      | Input clock                                                       |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|         10 | DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK                                                      | Input clock                                                       |
+------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_ccdebugss0:


Clocks for CCDEBUGSS0 Device
----------------------------

Device: :ref:`AM6_DEV_CCDEBUGSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 66)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_CCDEBUGSS0_BUS_ATB1_CLK | Input clock |
+------------+-----------------------------+-------------+
|          1 | DEV_CCDEBUGSS0_BUS_ATB0_CLK | Input clock |
+------------+-----------------------------+-------------+
|          2 | DEV_CCDEBUGSS0_BUS_SYS_CLK  | Input clock |
+------------+-----------------------------+-------------+
|          3 | DEV_CCDEBUGSS0_BUS_DBG_CLK  | Input clock |
+------------+-----------------------------+-------------+
|          4 | DEV_CCDEBUGSS0_BUS_CFG_CLK  | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cmpevent_intrtr0:


Clocks for CMPEVENT_INTRTR0 Device
----------------------------------

Device: :ref:`AM6_DEV_CMPEVENT_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 3)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_a53_0:


Clocks for COMPUTE_CLUSTER_A53_0 Device
---------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_A53_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 202)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_a53_1:


Clocks for COMPUTE_CLUSTER_A53_1 Device
---------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_A53_1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 203)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_a53_2:


Clocks for COMPUTE_CLUSTER_A53_2 Device
---------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_A53_2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 204)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_a53_3:


Clocks for COMPUTE_CLUSTER_A53_3 Device
---------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_A53_3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 205)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_cpac0:


Clocks for COMPUTE_CLUSTER_CPAC0 Device
---------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_cpac1:


Clocks for COMPUTE_CLUSTER_CPAC1 Device
---------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_cpac_pbist0:


Clocks for COMPUTE_CLUSTER_CPAC_PBIST0 Device
---------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_cpac_pbist1:


Clocks for COMPUTE_CLUSTER_CPAC_PBIST1 Device
---------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_msmc0:


Clocks for COMPUTE_CLUSTER_MSMC0 Device
---------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_MSMC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 196)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          2 | DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_compute_cluster_pbist0:


Clocks for COMPUTE_CLUSTER_PBIST0 Device
----------------------------------------

Device: :ref:`AM6_DEV_COMPUTE_CLUSTER_PBIST0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 197)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------+-------------+
|   Clock ID | Name                                             | Function    |
+============+==================================================+=============+
|          0 | DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK | Input clock |
+------------+--------------------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK | Input clock |
+------------+--------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_aggr0:


Clocks for CPT2_AGGR0 Device
----------------------------

Device: :ref:`AM6_DEV_CPT2_AGGR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 6)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_CPT2_AGGR0_BUS_VCLK_CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_cal0_0:


Clocks for CPT2_PROBE_VBUSM_MAIN_CAL0_0 Device
----------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 213)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------+-------------+
|   Clock ID | Name                                           | Function    |
+============+================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK  | Input clock |
+------------+------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK | Input clock |
+------------+------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_dss_2:


Clocks for CPT2_PROBE_VBUSM_MAIN_DSS_2 Device
---------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 214)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------+-------------+
|   Clock ID | Name                                          | Function    |
+============+===============================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK  | Input clock |
+------------+-----------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK | Input clock |
+------------+-----------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_navddrhi_5:


Clocks for CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 Device
--------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 <soc_doc_am6_public_devices_desc_device_list>` (ID = 211)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------+-------------+
|   Clock ID | Name                                               | Function    |
+============+====================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK  | Input clock |
+------------+----------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK | Input clock |
+------------+----------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_navddrlo_6:


Clocks for CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 Device
--------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 <soc_doc_am6_public_devices_desc_device_list>` (ID = 212)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------+-------------+
|   Clock ID | Name                                               | Function    |
+============+====================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK  | Input clock |
+------------+----------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK | Input clock |
+------------+----------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_navsramhi_3:


Clocks for CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 Device
---------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 209)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------+-------------+
|   Clock ID | Name                                                | Function    |
+============+=====================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK  | Input clock |
+------------+-----------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK | Input clock |
+------------+-----------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_main_navsramlo_4:


Clocks for CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 Device
---------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 <soc_doc_am6_public_devices_desc_device_list>` (ID = 206)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------+-------------+
|   Clock ID | Name                                                | Function    |
+============+=====================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK  | Input clock |
+------------+-----------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK | Input clock |
+------------+-----------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_mcu_export_slv_0:


Clocks for CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 Device
---------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 208)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------+-------------+
|   Clock ID | Name                                                | Function    |
+============+=====================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK  | Input clock |
+------------+-----------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK | Input clock |
+------------+-----------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_mcu_fss_s0_2:


Clocks for CPT2_PROBE_VBUSM_MCU_FSS_S0_2 Device
-----------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 215)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------+-------------+
|   Clock ID | Name                                            | Function    |
+============+=================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK  | Input clock |
+------------+-------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK | Input clock |
+------------+-------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_mcu_fss_s1_3:


Clocks for CPT2_PROBE_VBUSM_MCU_FSS_S1_3 Device
-----------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 207)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------+-------------+
|   Clock ID | Name                                            | Function    |
+============+=================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK  | Input clock |
+------------+-------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK | Input clock |
+------------+-------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_cpt2_probe_vbusm_mcu_sram_slv_1:


Clocks for CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 Device
-------------------------------------------------

Device: :ref:`AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 210)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------+-------------+
|   Clock ID | Name                                              | Function    |
+============+===================================================+=============+
|          0 | DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK  | Input clock |
+------------+---------------------------------------------------+-------------+
|          1 | DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK | Input clock |
+------------+---------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ctrl_mmr0:


Clocks for CTRL_MMR0 Device
---------------------------

Device: :ref:`AM6_DEV_CTRL_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 99)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_CTRL_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc0:


Clocks for DCC0 Device
----------------------

Device: :ref:`AM6_DEV_DCC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 9)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC0_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC0_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC0_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC0_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC0_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC0_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC0_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC0_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC0_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC0_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC0_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC0_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc1:


Clocks for DCC1 Device
----------------------

Device: :ref:`AM6_DEV_DCC1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 10)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC1_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC1_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC1_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC1_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC1_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC1_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC1_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC1_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC1_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC1_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC1_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC1_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_DCC1_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc2:


Clocks for DCC2 Device
----------------------

Device: :ref:`AM6_DEV_DCC2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 11)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC2_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC2_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC2_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC2_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC2_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC2_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC2_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC2_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC2_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC2_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC2_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC2_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_DCC2_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc3:


Clocks for DCC3 Device
----------------------

Device: :ref:`AM6_DEV_DCC3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 12)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC3_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC3_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC3_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC3_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC3_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC3_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC3_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC3_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC3_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC3_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC3_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC3_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc4:


Clocks for DCC4 Device
----------------------

Device: :ref:`AM6_DEV_DCC4 <soc_doc_am6_public_devices_desc_device_list>` (ID = 13)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC4_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC4_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC4_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC4_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC4_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC4_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC4_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC4_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC4_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC4_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC4_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC4_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc5:


Clocks for DCC5 Device
----------------------

Device: :ref:`AM6_DEV_DCC5 <soc_doc_am6_public_devices_desc_device_list>` (ID = 14)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC5_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC5_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC5_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC5_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC5_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC5_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC5_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC5_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC5_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC5_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC5_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC5_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_DCC5_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc6:


Clocks for DCC6 Device
----------------------

Device: :ref:`AM6_DEV_DCC6 <soc_doc_am6_public_devices_desc_device_list>` (ID = 15)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC6_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC6_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC6_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC6_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC6_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC6_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC6_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC6_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC6_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC6_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC6_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC6_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_DCC6_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dcc7:


Clocks for DCC7 Device
----------------------

Device: :ref:`AM6_DEV_DCC7 <soc_doc_am6_public_devices_desc_device_list>` (ID = 16)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DCC7_BUS_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_DCC7_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_DCC7_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_DCC7_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_DCC7_BUS_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_DCC7_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_DCC7_BUS_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_DCC7_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_DCC7_BUS_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_DCC7_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_DCC7_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_DCC7_BUS_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_DCC7_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ddrss0:


Clocks for DDRSS0 Device
------------------------

Device: :ref:`AM6_DEV_DDRSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 20)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+-------------+
|   Clock ID | Name                                                                         | Function    |
+============+==============================================================================+=============+
|          0 | DEV_DDRSS0_BUS_DDRSS_VBUS_CLK                                                | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          1 | DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK                                              | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          2 | DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          3 | DEV_DDRSS0_BUS_DDRSS_TCLK                                                    | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          4 | DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          5 | DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          6 | DEV_DDRSS0_BUS_DDRSS_CFG_CLK                                                 | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          7 | DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          8 | DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          9 | DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_debugss0:


Clocks for DEBUGSS0 Device
--------------------------

Device: :ref:`AM6_DEV_DEBUGSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 68)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_DEBUGSS0_BUS_ATB1_CLK | Input clock |
+------------+---------------------------+-------------+
|          1 | DEV_DEBUGSS0_BUS_ATB5_CLK | Input clock |
+------------+---------------------------+-------------+
|          2 | DEV_DEBUGSS0_BUS_ATB0_CLK | Input clock |
+------------+---------------------------+-------------+
|          3 | DEV_DEBUGSS0_BUS_SYS_CLK  | Input clock |
+------------+---------------------------+-------------+
|          4 | DEV_DEBUGSS0_BUS_ATB4_CLK | Input clock |
+------------+---------------------------+-------------+
|          5 | DEV_DEBUGSS0_BUS_CFG_CLK  | Input clock |
+------------+---------------------------+-------------+
|          6 | DEV_DEBUGSS0_BUS_ATB2_CLK | Input clock |
+------------+---------------------------+-------------+
|          7 | DEV_DEBUGSS0_BUS_DBG_CLK  | Input clock |
+------------+---------------------------+-------------+
|          8 | DEV_DEBUGSS0_BUS_ATB3_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_debugss_wrap0:


Clocks for DEBUGSS_WRAP0 Device
-------------------------------

Device: :ref:`AM6_DEV_DEBUGSS_WRAP0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 21)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK   | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_DEBUGSS_WRAP0_BUS_ATB_CLK    | Input clock |
+------------+----------------------------------+-------------+
|          2 | DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK | Input clock |
+------------+----------------------------------+-------------+
|          3 | DEV_DEBUGSS_WRAP0_BUS_CORE_CLK   | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_debugsuspendrtr0:


Clocks for DEBUGSUSPENDRTR0 Device
----------------------------------

Device: :ref:`AM6_DEV_DEBUGSUSPENDRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 81)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dftss0:


Clocks for DFTSS0 Device
------------------------

Device: :ref:`AM6_DEV_DFTSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 117)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_DFTSS0_BUS_VBUSP_CLK_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_dss0:


Clocks for DSS0 Device
----------------------

Device: :ref:`AM6_DEV_DSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 67)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                           | Function                                               |
+============+================================================================+========================================================+
|          0 | DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0                 | Input clock                                            |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_DSS0_BUS_DSS_FUNC_CLK                                      | Input clock                                            |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_DSS0_BUS_DPI_1_IN_CLK                                      | Input muxed clock                                      |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07                 | Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT | Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1                  | Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0                 | Input clock                                            |
+------------+----------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_DSS0_BUS_DPI_1_OUT_CLK                                     | Output clock                                           |
+------------+----------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_debug2dmsc_vd:


Clocks for DUMMY_IP_LPSC_DEBUG2DMSC_VD Device
---------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_dmsc_vd:


Clocks for DUMMY_IP_LPSC_DMSC_VD Device
---------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_emif_data_vd:


Clocks for DUMMY_IP_LPSC_EMIF_DATA_VD Device
--------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_main2mcu_vd:


Clocks for DUMMY_IP_LPSC_MAIN2MCU_VD Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_mcu2main_infra_vd:


Clocks for DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD Device
-------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_mcu2main_vd:


Clocks for DUMMY_IP_LPSC_MCU2MAIN_VD Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_mcu2wkup_vd:


Clocks for DUMMY_IP_LPSC_MCU2WKUP_VD Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_wkup2main_infra_vd:


Clocks for DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD Device
--------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_dummy_ip_lpsc_wkup2mcu_vd:


Clocks for DUMMY_IP_LPSC_WKUP2MCU_VD Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_ecap0:


Clocks for ECAP0 Device
-----------------------

Device: :ref:`AM6_DEV_ECAP0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 39)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_ECAP0_BUS_VBUS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ecc_aggr0:


Clocks for ECC_AGGR0 Device
---------------------------

Device: :ref:`AM6_DEV_ECC_AGGR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 86)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_ECC_AGGR0_BUS_AGGR_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ecc_aggr1:


Clocks for ECC_AGGR1 Device
---------------------------

Device: :ref:`AM6_DEV_ECC_AGGR1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 87)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_ECC_AGGR1_BUS_AGGR_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ecc_aggr2:


Clocks for ECC_AGGR2 Device
---------------------------

Device: :ref:`AM6_DEV_ECC_AGGR2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 88)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_ECC_AGGR2_BUS_AGGR_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_efuse0:


Clocks for EFUSE0 Device
------------------------

Device: :ref:`AM6_DEV_EFUSE0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 69)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm0:


Clocks for EHRPWM0 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 40)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM0_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm1:


Clocks for EHRPWM1 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 41)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM1_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm2:


Clocks for EHRPWM2 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 42)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM2_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm3:


Clocks for EHRPWM3 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 43)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM3_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm4:


Clocks for EHRPWM4 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM4 <soc_doc_am6_public_devices_desc_device_list>` (ID = 44)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM4_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_ehrpwm5:


Clocks for EHRPWM5 Device
-------------------------

Device: :ref:`AM6_DEV_EHRPWM5 <soc_doc_am6_public_devices_desc_device_list>` (ID = 45)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_EHRPWM5_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_elm0:


Clocks for ELM0 Device
----------------------

Device: :ref:`AM6_DEV_ELM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 46)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_ELM0_BUS_VBUSP_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_eqep0:


Clocks for EQEP0 Device
-----------------------

Device: :ref:`AM6_DEV_EQEP0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 49)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_EQEP0_BUS_VBUS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_eqep1:


Clocks for EQEP1 Device
-----------------------

Device: :ref:`AM6_DEV_EQEP1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 50)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_EQEP1_BUS_VBUS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_eqep2:


Clocks for EQEP2 Device
-----------------------

Device: :ref:`AM6_DEV_EQEP2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 51)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_EQEP2_BUS_VBUS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_esm0:


Clocks for ESM0 Device
----------------------

Device: :ref:`AM6_DEV_ESM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 52)

Following is a mapping of Clocks IDs to function:

+------------+------------------+-------------+
|   Clock ID | Name             | Function    |
+============+==================+=============+
|          0 | DEV_ESM0_BUS_CLK | Input clock |
+------------+------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_fss_mcu_0:


Clocks for FSS_MCU_0 Device
---------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_gic0:


Clocks for GIC0 Device
----------------------

Device: :ref:`AM6_DEV_GIC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 56)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_GIC0_BUS_VCLK_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gpio0:


Clocks for GPIO0 Device
-----------------------

Device: :ref:`AM6_DEV_GPIO0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 57)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_GPIO0_BUS_MMR_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gpio1:


Clocks for GPIO1 Device
-----------------------

Device: :ref:`AM6_DEV_GPIO1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 58)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_GPIO1_BUS_MMR_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gpiomux_intrtr0:


Clocks for GPIOMUX_INTRTR0 Device
---------------------------------

Device: :ref:`AM6_DEV_GPIOMUX_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 100)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gpmc0:


Clocks for GPMC0 Device
-----------------------

Device: :ref:`AM6_DEV_GPMC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 60)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                            |
+============+==============================================================================+=====================================================+
|          0 | DEV_GPMC0_BUS_FUNC_CLK                                                       | Input muxed clock                                   |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3     | Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2     | Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4 | Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_GPMC0_BUS_PI_GPMC_RET_CLK                                                | Input clock                                         |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_GPMC0_BUS_VBUSP_CLK                                                      | Input clock                                         |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_GPMC0_BUS_PO_GPMC_DEV_CLK                                                | Output clock                                        |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_gpu0:


Clocks for GPU0 Device
----------------------

Device: :ref:`AM6_DEV_GPU0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 65)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_GPU0_BUS_MEM_CLK      | Input clock |
+------------+---------------------------+-------------+
|          1 | DEV_GPU0_BUS_HYD_CORE_CLK | Input clock |
+------------+---------------------------+-------------+
|          2 | DEV_GPU0_BUS_SGX_CORE_CLK | Input clock |
+------------+---------------------------+-------------+
|          3 | DEV_GPU0_BUS_SYS_CLK      | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gs80prg_mcu_wrap_wkup_0:


Clocks for GS80PRG_MCU_WRAP_WKUP_0 Device
-----------------------------------------

Device: :ref:`AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 232)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK     | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gs80prg_soc_wrap_wkup_0:


Clocks for GS80PRG_SOC_WRAP_WKUP_0 Device
-----------------------------------------

Device: :ref:`AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 231)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK     | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_gtc0:


Clocks for GTC0 Device
----------------------

Device: :ref:`AM6_DEV_GTC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 61)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                            |
+============+================================================================================+=====================================================+
|          0 | DEV_GTC0_BUS_VBUSP_CLK                                                         | Input muxed clock                                   |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                 | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                 | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK                 | Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_i2c0:


Clocks for I2C0 Device
----------------------

Device: :ref:`AM6_DEV_I2C0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 110)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_I2C0_BUS_CLK       | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_I2C0_BUS_PISYS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_i2c1:


Clocks for I2C1 Device
----------------------

Device: :ref:`AM6_DEV_I2C1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 111)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_I2C1_BUS_CLK       | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_I2C1_BUS_PISYS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_i2c2:


Clocks for I2C2 Device
----------------------

Device: :ref:`AM6_DEV_I2C2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 112)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_I2C2_BUS_CLK       | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_I2C2_BUS_PISYS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_i2c3:


Clocks for I2C3 Device
----------------------

Device: :ref:`AM6_DEV_I2C3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 113)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_I2C3_BUS_CLK       | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_I2C3_BUS_PISYS_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_icemelter_wkup_0:


Clocks for ICEMELTER_WKUP_0 Device
----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_k3_arm_atb_funnel_3_32_mcu_0:


Clocks for K3_ARM_ATB_FUNNEL_3_32_MCU_0 Device
----------------------------------------------

Device: :ref:`AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 217)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------+-------------+
|   Clock ID | Name                                         | Function    |
+============+==============================================+=============+
|          0 | DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK | Input clock |
+------------+----------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_k3_led_main_0:


Clocks for K3_LED_MAIN_0 Device
-------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_main2mcu_lvl_intrtr0:


Clocks for MAIN2MCU_LVL_INTRTR0 Device
--------------------------------------

Device: :ref:`AM6_DEV_MAIN2MCU_LVL_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 97)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------+-------------+
|   Clock ID | Name                                  | Function    |
+============+=======================================+=============+
|          0 | DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+---------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_main2mcu_pls_intrtr0:


Clocks for MAIN2MCU_PLS_INTRTR0 Device
--------------------------------------

Device: :ref:`AM6_DEV_MAIN2MCU_PLS_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 98)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------+-------------+
|   Clock ID | Name                                  | Function    |
+============+=======================================+=============+
|          0 | DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+---------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcasp0:


Clocks for MCASP0 Device
------------------------

Device: :ref:`AM6_DEV_MCASP0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 104)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                            |
+============+================================================================================+=====================================================+
|          0 | DEV_MCASP0_BUS_AUX_CLK                                                         | Input muxed clock                                   |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0                      | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                      | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                      | Parent input clock option to DEV_MCASP0_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          9 | DEV_MCASP0_BUS_VBUSP_CLK                                                       | Input clock                                         |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcasp1:


Clocks for MCASP1 Device
------------------------

Device: :ref:`AM6_DEV_MCASP1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 105)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                            |
+============+================================================================================+=====================================================+
|          0 | DEV_MCASP1_BUS_AUX_CLK                                                         | Input muxed clock                                   |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1                      | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                      | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                      | Parent input clock option to DEV_MCASP1_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          9 | DEV_MCASP1_BUS_VBUSP_CLK                                                       | Input clock                                         |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcasp2:


Clocks for MCASP2 Device
------------------------

Device: :ref:`AM6_DEV_MCASP2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 106)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                            |
+============+================================================================================+=====================================================+
|          0 | DEV_MCASP2_BUS_AUX_CLK                                                         | Input muxed clock                                   |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2                      | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                      | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                      | Parent input clock option to DEV_MCASP2_BUS_AUX_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+
|          9 | DEV_MCASP2_BUS_VBUSP_CLK                                                       | Input clock                                         |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcspi0:


Clocks for MCSPI0 Device
------------------------

Device: :ref:`AM6_DEV_MCSPI0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 137)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCSPI0_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCSPI0_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCSPI0_BUS_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCSPI0_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcspi1:


Clocks for MCSPI1 Device
------------------------

Device: :ref:`AM6_DEV_MCSPI1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 138)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCSPI1_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCSPI1_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCSPI1_BUS_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCSPI1_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcspi2:


Clocks for MCSPI2 Device
------------------------

Device: :ref:`AM6_DEV_MCSPI2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 139)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCSPI2_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCSPI2_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCSPI2_BUS_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCSPI2_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcspi3:


Clocks for MCSPI3 Device
------------------------

Device: :ref:`AM6_DEV_MCSPI3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 140)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCSPI3_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCSPI3_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCSPI3_BUS_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCSPI3_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcspi4:


Clocks for MCSPI4 Device
------------------------

Device: :ref:`AM6_DEV_MCSPI4 <soc_doc_am6_public_devices_desc_device_list>` (ID = 141)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCSPI4_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCSPI4_BUS_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCSPI4_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCSPI4_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_adc0:


Clocks for MCU_ADC0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_ADC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 0)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                              |
+============+===============================================================================+=======================================================+
|          0 | DEV_MCU_ADC0_BUS_VBUS_CLK                                                     | Input clock                                           |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          1 | DEV_MCU_ADC0_BUS_SYS_CLK                                                      | Input clock                                           |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          2 | DEV_MCU_ADC0_BUS_ADC_CLK                                                      | Input muxed clock                                     |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          3 | DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK       | Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          4 | DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK | Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          5 | DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          6 | DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_adc1:


Clocks for MCU_ADC1 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_ADC1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 1)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                              |
+============+===============================================================================+=======================================================+
|          0 | DEV_MCU_ADC1_BUS_VBUS_CLK                                                     | Input clock                                           |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          1 | DEV_MCU_ADC1_BUS_SYS_CLK                                                      | Input clock                                           |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          2 | DEV_MCU_ADC1_BUS_ADC_CLK                                                      | Input muxed clock                                     |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          3 | DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK       | Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          4 | DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK | Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          5 | DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+
|          6 | DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK |
+------------+-------------------------------------------------------------------------------+-------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_armss0:


Clocks for MCU_ARMSS0 Device
----------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_armss0_cpu0:


Clocks for MCU_ARMSS0_CPU0 Device
---------------------------------

Device: :ref:`AM6_DEV_MCU_ARMSS0_CPU0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 159)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|   Clock ID | Name                                                                                          | Function                                                             |
+============+===============================================================================================+======================================================================+
|          0 | DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK                                                         | Input clock                                                          |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          1 | DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE                                                       | Input muxed clock                                                    |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          2 | DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          3 | DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK                                                               | Input muxed clock                                                    |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          4 | DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK          | Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK         |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          5 | DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2         | Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK         |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_armss0_cpu1:


Clocks for MCU_ARMSS0_CPU1 Device
---------------------------------

Device: :ref:`AM6_DEV_MCU_ARMSS0_CPU1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 245)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|   Clock ID | Name                                                                                          | Function                                                             |
+============+===============================================================================================+======================================================================+
|          0 | DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK                                                         | Input clock                                                          |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          1 | DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE                                                       | Input muxed clock                                                    |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          2 | DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          3 | DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK                                                               | Input muxed clock                                                    |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          4 | DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK          | Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK         |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+
|          5 | DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2         | Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK         |
+------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_cbass0:


Clocks for MCU_CBASS0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_CBASS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 89)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------+-------------+
|   Clock ID | Name                                 | Function    |
+============+======================================+=============+
|          0 | DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK | Input clock |
+------------+--------------------------------------+-------------+
|          1 | DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK | Input clock |
+------------+--------------------------------------+-------------+
|          2 | DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK | Input clock |
+------------+--------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_cbass_debug0:


Clocks for MCU_CBASS_DEBUG0 Device
----------------------------------

Device: :ref:`AM6_DEV_MCU_CBASS_DEBUG0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 90)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------+-------------+
|   Clock ID | Name                                       | Function    |
+============+============================================+=============+
|          0 | DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK | Input clock |
+------------+--------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_cbass_fw0:


Clocks for MCU_CBASS_FW0 Device
-------------------------------

Device: :ref:`AM6_DEV_MCU_CBASS_FW0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 91)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_cpsw0:


Clocks for MCU_CPSW0 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_CPSW0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 5)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                             | Function                                                       |
+============+==================================================================================+================================================================+
|          0 | DEV_MCU_CPSW0_BUS_GMII1_MR_CLK                                                   | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK                                              | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK                                                   | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_CPSW0_BUS_GMII1_MT_CLK                                                   | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK                                                | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK                                               | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK                                                | Input muxed clock                                              |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          7 | DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5 | Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT        | Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_CPSW0_BUS_GMII_RFT_CLK                                                   | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+
|         10 | DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK                                                   | Input clock                                                    |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_cpt2_aggr0:


Clocks for MCU_CPT2_AGGR0 Device
--------------------------------

Device: :ref:`AM6_DEV_MCU_CPT2_AGGR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 7)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------+-------------+
|   Clock ID | Name                            | Function    |
+============+=================================+=============+
|          0 | DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK | Input clock |
+------------+---------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_ctrl_mmr0:


Clocks for MCU_CTRL_MMR0 Device
-------------------------------

Device: :ref:`AM6_DEV_MCU_CTRL_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 107)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------+-------------+
|   Clock ID | Name                            | Function    |
+============+=================================+=============+
|          0 | DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+---------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_dcc0:


Clocks for MCU_DCC0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_DCC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 17)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+----------------------------------+-------------+
|          2 | DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+----------------------------------+-------------+
|          3 | DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+----------------------------------+-------------+
|          4 | DEV_MCU_DCC0_BUS_VBUS_CLK        | Input clock |
+------------+----------------------------------+-------------+
|          5 | DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+----------------------------------+-------------+
|          6 | DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK | Input clock |
+------------+----------------------------------+-------------+
|          7 | DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+----------------------------------+-------------+
|          8 | DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK | Input clock |
+------------+----------------------------------+-------------+
|          9 | DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+----------------------------------+-------------+
|         10 | DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+----------------------------------+-------------+
|         11 | DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK | Input clock |
+------------+----------------------------------+-------------+
|         12 | DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_dcc1:


Clocks for MCU_DCC1 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_DCC1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 18)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+----------------------------------+-------------+
|          2 | DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+----------------------------------+-------------+
|          3 | DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+----------------------------------+-------------+
|          4 | DEV_MCU_DCC1_BUS_VBUS_CLK        | Input clock |
+------------+----------------------------------+-------------+
|          5 | DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+----------------------------------+-------------+
|          6 | DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK | Input clock |
+------------+----------------------------------+-------------+
|          7 | DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+----------------------------------+-------------+
|          8 | DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK | Input clock |
+------------+----------------------------------+-------------+
|          9 | DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+----------------------------------+-------------+
|         10 | DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+----------------------------------+-------------+
|         11 | DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK | Input clock |
+------------+----------------------------------+-------------+
|         12 | DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_dcc2:


Clocks for MCU_DCC2 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_DCC2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 19)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK | Input clock |
+------------+----------------------------------+-------------+
|          2 | DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK | Input clock |
+------------+----------------------------------+-------------+
|          3 | DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK | Input clock |
+------------+----------------------------------+-------------+
|          4 | DEV_MCU_DCC2_BUS_VBUS_CLK        | Input clock |
+------------+----------------------------------+-------------+
|          5 | DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK | Input clock |
+------------+----------------------------------+-------------+
|          6 | DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK | Input clock |
+------------+----------------------------------+-------------+
|          7 | DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK | Input clock |
+------------+----------------------------------+-------------+
|          8 | DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK | Input clock |
+------------+----------------------------------+-------------+
|          9 | DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK | Input clock |
+------------+----------------------------------+-------------+
|         10 | DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK | Input clock |
+------------+----------------------------------+-------------+
|         11 | DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK | Input clock |
+------------+----------------------------------+-------------+
|         12 | DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_debugss0:


Clocks for MCU_DEBUGSS0 Device
------------------------------

Device: :ref:`AM6_DEV_MCU_DEBUGSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 71)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_MCU_DEBUGSS0_BUS_ATB1_CLK | Input clock |
+------------+-------------------------------+-------------+
|          1 | DEV_MCU_DEBUGSS0_BUS_ATB0_CLK | Input clock |
+------------+-------------------------------+-------------+
|          2 | DEV_MCU_DEBUGSS0_BUS_SYS_CLK  | Input clock |
+------------+-------------------------------+-------------+
|          3 | DEV_MCU_DEBUGSS0_BUS_CFG_CLK  | Input clock |
+------------+-------------------------------+-------------+
|          4 | DEV_MCU_DEBUGSS0_BUS_ATB2_CLK | Input clock |
+------------+-------------------------------+-------------+
|          5 | DEV_MCU_DEBUGSS0_BUS_DBG_CLK  | Input clock |
+------------+-------------------------------+-------------+
|          6 | DEV_MCU_DEBUGSS0_BUS_ATB3_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_ecc_aggr0:


Clocks for MCU_ECC_AGGR0 Device
-------------------------------

Device: :ref:`AM6_DEV_MCU_ECC_AGGR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 92)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_ecc_aggr1:


Clocks for MCU_ECC_AGGR1 Device
-------------------------------

Device: :ref:`AM6_DEV_MCU_ECC_AGGR1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 93)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_efuse0:


Clocks for MCU_EFUSE0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_EFUSE0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 72)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_esm0:


Clocks for MCU_ESM0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_ESM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 53)

Following is a mapping of Clocks IDs to function:

+------------+----------------------+-------------+
|   Clock ID | Name                 | Function    |
+============+======================+=============+
|          0 | DEV_MCU_ESM0_BUS_CLK | Input clock |
+------------+----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_fss0_fsas_0:


Clocks for MCU_FSS0_FSAS_0 Device
---------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_fss0_hyperbus0:


Clocks for MCU_FSS0_HYPERBUS0 Device
------------------------------------

Device: :ref:`AM6_DEV_MCU_FSS0_HYPERBUS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 247)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------+-------------+
|   Clock ID | Name                                         | Function    |
+============+==============================================+=============+
|          0 | DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK | Input clock |
+------------+----------------------------------------------+-------------+
|          1 | DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK     | Input clock |
+------------+----------------------------------------------+-------------+
|          2 | DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK     | Input clock |
+------------+----------------------------------------------+-------------+
|          3 | DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK           | Input clock |
+------------+----------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_fss0_ospi_0:


Clocks for MCU_FSS0_OSPI_0 Device
---------------------------------

Device: :ref:`AM6_DEV_MCU_FSS0_OSPI_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 248)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|   Clock ID | Name                                                                                       | Function                                                           |
+============+============================================================================================+====================================================================+
|          0 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK                                                      | Input muxed clock                                                  |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          1 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          2 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          3 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK                                                      | Input muxed clock                                                  |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          4 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT                  | Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          5 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK            | Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          6 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK                                                      | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          7 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK                                                       | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          8 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK                                                      | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          9 | DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK                                                      | Output clock                                                       |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_fss0_ospi_1:


Clocks for MCU_FSS0_OSPI_1 Device
---------------------------------

Device: :ref:`AM6_DEV_MCU_FSS0_OSPI_1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 249)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|   Clock ID | Name                                                                                       | Function                                                           |
+============+============================================================================================+====================================================================+
|          0 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK                                                      | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          1 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK                                                      | Input muxed clock                                                  |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          2 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT                  | Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          3 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK            | Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          4 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK                                                      | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          5 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK                                                       | Input clock                                                        |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          6 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK                                                      | Input muxed clock                                                  |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          7 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          8 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+
|          9 | DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK                                                      | Output clock                                                       |
+------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_i2c0:


Clocks for MCU_I2C0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_I2C0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 114)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_MCU_I2C0_BUS_CLK       | Input clock |
+------------+----------------------------+-------------+
|          1 | DEV_MCU_I2C0_BUS_PISYS_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_mcan0:


Clocks for MCU_MCAN0 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_MCAN0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 102)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK  | Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2 | Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2 | Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_mcan1:


Clocks for MCU_MCAN1 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_MCAN1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 103)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK  | Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2 | Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2 | Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_mcspi0:


Clocks for MCU_MCSPI0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_MCSPI0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 142)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+--------------+
|   Clock ID | Name                              | Function     |
+============+===================================+==============+
|          0 | DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-----------------------------------+--------------+
|          1 | DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-----------------------------------+--------------+
|          2 | DEV_MCU_MCSPI0_BUS_VBUSP_CLK      | Input clock  |
+------------+-----------------------------------+--------------+
|          3 | DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-----------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_mcspi1:


Clocks for MCU_MCSPI1 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_MCSPI1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 143)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+--------------+
|   Clock ID | Name                              | Function     |
+============+===================================+==============+
|          0 | DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-----------------------------------+--------------+
|          1 | DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-----------------------------------+--------------+
|          2 | DEV_MCU_MCSPI1_BUS_VBUSP_CLK      | Input clock  |
+------------+-----------------------------------+--------------+
|          3 | DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-----------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_mcspi2:


Clocks for MCU_MCSPI2 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_MCSPI2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 144)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+--------------+
|   Clock ID | Name                              | Function     |
+============+===================================+==============+
|          0 | DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK  | Input clock  |
+------------+-----------------------------------+--------------+
|          1 | DEV_MCU_MCSPI2_BUS_VBUSP_CLK      | Input clock  |
+------------+-----------------------------------+--------------+
|          2 | DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK | Input clock  |
+------------+-----------------------------------+--------------+
|          3 | DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK | Output clock |
+------------+-----------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_msram0:


Clocks for MCU_MSRAM0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_MSRAM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 116)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_MCU_MSRAM0_BUS_CCLK_CLK | Input clock |
+------------+-----------------------------+-------------+
|          1 | DEV_MCU_MSRAM0_BUS_VCLK_CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0:


Clocks for MCU_NAVSS0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_NAVSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 119)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------+-------------+
|   Clock ID | Name                            | Function    |
+============+=================================+=============+
|          1 | DEV_MCU_NAVSS0_BUS_CPSW0CLK     | Input clock |
+------------+---------------------------------+-------------+
|          2 | DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK | Input clock |
+------------+---------------------------------+-------------+
|          3 | DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK | Input clock |
+------------+---------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_intr_aggr_0:


Clocks for MCU_NAVSS0_INTR_AGGR_0 Device
----------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_intr_router_0:


Clocks for MCU_NAVSS0_INTR_ROUTER_0 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_mcrc0:


Clocks for MCU_NAVSS0_MCRC0 Device
----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_proxy0:


Clocks for MCU_NAVSS0_PROXY0 Device
-----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_ringacc0:


Clocks for MCU_NAVSS0_RINGACC0 Device
-------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_navss0_udmap0:


Clocks for MCU_NAVSS0_UDMAP0 Device
-----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mcu_pbist0:


Clocks for MCU_PBIST0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_PBIST0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 75)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_MCU_PBIST0_BUS_CLK1_CLK | Input clock |
+------------+-----------------------------+-------------+
|          1 | DEV_MCU_PBIST0_BUS_CLK4_CLK | Input clock |
+------------+-----------------------------+-------------+
|          2 | DEV_MCU_PBIST0_BUS_CLK2_CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_pdma0:


Clocks for MCU_PDMA0 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_PDMA0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 125)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_MCU_PDMA0_BUS_VCLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_pdma1:


Clocks for MCU_PDMA1 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_PDMA1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 126)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_MCU_PDMA1_BUS_VCLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_pll_mmr0:


Clocks for MCU_PLL_MMR0 Device
------------------------------

Device: :ref:`AM6_DEV_MCU_PLL_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 108)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_psram0:


Clocks for MCU_PSRAM0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_PSRAM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 127)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_MCU_PSRAM0_BUS_CLK_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_rom0:


Clocks for MCU_ROM0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_ROM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 78)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_MCU_ROM0_BUS_CLK_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_rti0:


Clocks for MCU_RTI0 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_RTI0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 134)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                              |
+============+================================================================================+=======================================================+
|          0 | DEV_MCU_RTI0_BUS_RTI_CLK                                                       | Input muxed clock                                     |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          1 | DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          2 | DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          3 | DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          4 | DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          5 | DEV_MCU_RTI0_BUS_VBUSP_CLK                                                     | Input clock                                           |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_rti1:


Clocks for MCU_RTI1 Device
--------------------------

Device: :ref:`AM6_DEV_MCU_RTI1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 135)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                              |
+============+================================================================================+=======================================================+
|          0 | DEV_MCU_RTI1_BUS_RTI_CLK                                                       | Input muxed clock                                     |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          1 | DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          2 | DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          3 | DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          4 | DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+
|          5 | DEV_MCU_RTI1_BUS_VBUSP_CLK                                                     | Input clock                                           |
+------------+--------------------------------------------------------------------------------+-------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_sec_mmr0:


Clocks for MCU_SEC_MMR0 Device
------------------------------

Device: :ref:`AM6_DEV_MCU_SEC_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 109)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_timer0:


Clocks for MCU_TIMER0 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_TIMER0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 35)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK         | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_timer1:


Clocks for MCU_TIMER1 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_TIMER1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 36)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK         | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_timer2:


Clocks for MCU_TIMER2 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_TIMER2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 37)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK         | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_timer3:


Clocks for MCU_TIMER3 Device
----------------------------

Device: :ref:`AM6_DEV_MCU_TIMER3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 38)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                                    | Function                                                       |
+============+=========================================================================================+================================================================+
|          0 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK                                                       | Input muxed clock                                              |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK         | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK                                                       | Input clock                                                    |
+------------+-----------------------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mcu_uart0:


Clocks for MCU_UART0 Device
---------------------------

Device: :ref:`AM6_DEV_MCU_UART0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 149)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                |
+============+=================================================================================+=========================================================+
|          0 | DEV_MCU_UART0_BUS_FCLK_CLK                                                      | Input muxed clock                                       |
+------------+---------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK |
+------------+---------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5          | Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK |
+------------+---------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCU_UART0_BUS_VBUSP_CLK                                                     | Input clock                                             |
+------------+---------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_mmcsd0:


Clocks for MMCSD0 Device
------------------------

Device: :ref:`AM6_DEV_MMCSD0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 47)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK  | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mmcsd1:


Clocks for MMCSD1 Device
------------------------

Device: :ref:`AM6_DEV_MMCSD1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 48)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK  | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_mx_efuse_main_chain_main_0:


Clocks for MX_EFUSE_MAIN_CHAIN_MAIN_0 Device
--------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mx_efuse_mcu_chain_mcu_0:


Clocks for MX_EFUSE_MCU_CHAIN_MCU_0 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_mx_wakeup_reset_sync_wkup_0:


Clocks for MX_WAKEUP_RESET_SYNC_WKUP_0 Device
---------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0:


Clocks for NAVSS0 Device
------------------------

Device: :ref:`AM6_DEV_NAVSS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 118)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+-------------+
|   Clock ID | Name                                                                         | Function    |
+============+==============================================================================+=============+
|          1 | DEV_NAVSS0_BUS_ICSS_G2CLK                                                    | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          2 | DEV_NAVSS0_BUS_ICSS_G0CLK                                                    | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          3 | DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          4 | DEV_NAVSS0_BUS_MSMC0CLK                                                      | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          5 | DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          6 | DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                 | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          8 | DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|          9 | DEV_NAVSS0_BUS_PDMA_MAIN1CLK                                                 | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|         10 | DEV_NAVSS0_BUS_NBSS_VCLK                                                     | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|         11 | DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|         12 | DEV_NAVSS0_BUS_NBSS_VD2CLK                                                   | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|         13 | DEV_NAVSS0_BUS_ICSS_G1CLK                                                    | Input clock |
+------------+------------------------------------------------------------------------------+-------------+
|         14 | DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Input clock |
+------------+------------------------------------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_navss0_cpts0:


Clocks for NAVSS0_CPTS0 Device
------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_intr_router_0:


Clocks for NAVSS0_INTR_ROUTER_0 Device
--------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster0:


Clocks for NAVSS0_MAILBOX0_CLUSTER0 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster1:


Clocks for NAVSS0_MAILBOX0_CLUSTER1 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster10:


Clocks for NAVSS0_MAILBOX0_CLUSTER10 Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster11:


Clocks for NAVSS0_MAILBOX0_CLUSTER11 Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster2:


Clocks for NAVSS0_MAILBOX0_CLUSTER2 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster3:


Clocks for NAVSS0_MAILBOX0_CLUSTER3 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster4:


Clocks for NAVSS0_MAILBOX0_CLUSTER4 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster5:


Clocks for NAVSS0_MAILBOX0_CLUSTER5 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster6:


Clocks for NAVSS0_MAILBOX0_CLUSTER6 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster7:


Clocks for NAVSS0_MAILBOX0_CLUSTER7 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster8:


Clocks for NAVSS0_MAILBOX0_CLUSTER8 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mailbox0_cluster9:


Clocks for NAVSS0_MAILBOX0_CLUSTER9 Device
------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_mcrc0:


Clocks for NAVSS0_MCRC0 Device
------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_modss_inta0:


Clocks for NAVSS0_MODSS_INTA0 Device
------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_modss_inta1:


Clocks for NAVSS0_MODSS_INTA1 Device
------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_proxy0:


Clocks for NAVSS0_PROXY0 Device
-------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_pvu0:


Clocks for NAVSS0_PVU0 Device
-----------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_pvu1:


Clocks for NAVSS0_PVU1 Device
-----------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_ringacc0:


Clocks for NAVSS0_RINGACC0 Device
---------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_timer_mgr0:


Clocks for NAVSS0_TIMER_MGR0 Device
-----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_timer_mgr1:


Clocks for NAVSS0_TIMER_MGR1 Device
-----------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_udmap0:


Clocks for NAVSS0_UDMAP0 Device
-------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_navss0_udmass_inta0:


Clocks for NAVSS0_UDMASS_INTA0 Device
-------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_oldi_tx_core_main_0:


Clocks for OLDI_TX_CORE_MAIN_0 Device
-------------------------------------

Device: :ref:`AM6_DEV_OLDI_TX_CORE_MAIN_0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 216)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------+-------------+
|   Clock ID | Name                                                              | Function    |
+============+===================================================================+=============+
|          0 | DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK                          | Input clock |
+------------+-------------------------------------------------------------------+-------------+
|          1 | DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0 | Input clock |
+------------+-------------------------------------------------------------------+-------------+
|          2 | DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0 | Input clock |
+------------+-------------------------------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pbist0:


Clocks for PBIST0 Device
------------------------

Device: :ref:`AM6_DEV_PBIST0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 73)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_PBIST0_BUS_CLK1_CLK | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_PBIST0_BUS_CLK4_CLK | Input clock |
+------------+-------------------------+-------------+
|          2 | DEV_PBIST0_BUS_CLK2_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pbist1:


Clocks for PBIST1 Device
------------------------

Device: :ref:`AM6_DEV_PBIST1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 74)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_PBIST1_BUS_CLK1_CLK | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_PBIST1_BUS_CLK4_CLK | Input clock |
+------------+-------------------------+-------------+
|          2 | DEV_PBIST1_BUS_CLK2_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pcie0:


Clocks for PCIE0 Device
-----------------------

Device: :ref:`AM6_DEV_PCIE0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 120)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------------------+--------------+
|   Clock ID | Name                                                                                      | Function     |
+============+===========================================================================================+==============+
|          0 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          1 | DEV_PCIE0_BUS_PCIE_CBA_CLK                                                                | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          2 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          3 | DEV_PCIE0_BUS_PCIE_TXI0_CLK                                                               | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          4 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          5 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          6 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          7 | DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                 | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          8 | DEV_PCIE0_BUS_PCIE_TXR1_CLK                                                               | Output clock |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          9 | DEV_PCIE0_BUS_PCIE_TXR0_CLK                                                               | Output clock |
+------------+-------------------------------------------------------------------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_pcie1:


Clocks for PCIE1 Device
-----------------------

Device: :ref:`AM6_DEV_PCIE1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 121)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------------------+--------------+
|   Clock ID | Name                                                                                      | Function     |
+============+===========================================================================================+==============+
|          0 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          1 | DEV_PCIE1_BUS_PCIE_CBA_CLK                                                                | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          2 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          3 | DEV_PCIE1_BUS_PCIE_TXI0_CLK                                                               | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          4 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          5 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          6 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          7 | DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                 | Input clock  |
+------------+-------------------------------------------------------------------------------------------+--------------+
|          8 | DEV_PCIE1_BUS_PCIE_TXR0_CLK                                                               | Output clock |
+------------+-------------------------------------------------------------------------------------------+--------------+

.. _soc_doc_am65x_sr2_public_clks_pdma0:


Clocks for PDMA0 Device
-----------------------

Device: :ref:`AM6_DEV_PDMA0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 123)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_PDMA0_BUS_VCLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pdma1:


Clocks for PDMA1 Device
-----------------------

Device: :ref:`AM6_DEV_PDMA1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 124)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_PDMA1_BUS_VCLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pdma_debug0:


Clocks for PDMA_DEBUG0 Device
-----------------------------

Device: :ref:`AM6_DEV_PDMA_DEBUG0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 122)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_PDMA_DEBUG0_BUS_VCLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pllctrl0:


Clocks for PLLCTRL0 Device
--------------------------

Device: :ref:`AM6_DEV_PLLCTRL0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 76)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                                     |
+============+================================================================================+==============================================================+
|          0 | DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK                                           | Input clock                                                  |
+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+
|          1 | DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK                                                | Input clock                                                  |
+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+
|          2 | DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK                                                | Input muxed clock                                            |
+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+
|          3 | DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK | Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK |
+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+
|          4 | DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                  | Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK |
+------------+--------------------------------------------------------------------------------+--------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_pll_mmr0:


Clocks for PLL_MMR0 Device
--------------------------

Device: :ref:`AM6_DEV_PLL_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 101)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_PLL_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_pru_icssg0:


Clocks for PRU_ICSSG0 Device
----------------------------

Device: :ref:`AM6_DEV_PRU_ICSSG0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 62)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                                | Function                                                 |
+============+=====================================================================================+==========================================================+
|          0 | DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_PRU_ICSSG0_BUS_VCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          4 | DEV_PRU_ICSSG0_BUS_UCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          5 | DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          6 | DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          8 | DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK                                                | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          9 | DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK                                                 | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         10 | DEV_PRU_ICSSG0_BUS_IEP_CLK                                                          | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         11 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK     | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         12 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         13 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                  | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         14 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                      | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         15 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                   | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         16 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                       | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         17 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         18 | DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         19 | DEV_PRU_ICSSG0_BUS_CORE_CLK                                                         | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         20 | DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         21 | DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_pru_icssg1:


Clocks for PRU_ICSSG1 Device
----------------------------

Device: :ref:`AM6_DEV_PRU_ICSSG1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 63)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                                | Function                                                 |
+============+=====================================================================================+==========================================================+
|          0 | DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_PRU_ICSSG1_BUS_VCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          4 | DEV_PRU_ICSSG1_BUS_UCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          5 | DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          6 | DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          8 | DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK                                                | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          9 | DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK                                                 | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         10 | DEV_PRU_ICSSG1_BUS_IEP_CLK                                                          | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         11 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK     | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         12 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         13 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                  | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         14 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                      | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         15 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                   | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         16 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                       | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         17 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         18 | DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         19 | DEV_PRU_ICSSG1_BUS_CORE_CLK                                                         | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         20 | DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         21 | DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_pru_icssg2:


Clocks for PRU_ICSSG2 Device
----------------------------

Device: :ref:`AM6_DEV_PRU_ICSSG2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 64)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                                | Function                                                 |
+============+=====================================================================================+==========================================================+
|          0 | DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_PRU_ICSSG2_BUS_VCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          4 | DEV_PRU_ICSSG2_BUS_UCLK_CLK                                                         | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          5 | DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          6 | DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK                                                  | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          8 | DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK                                                | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|          9 | DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK                                                 | Input clock                                              |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         10 | DEV_PRU_ICSSG2_BUS_IEP_CLK                                                          | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         11 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK     | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         12 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK  | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         13 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT                  | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         14 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                      | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         15 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                   | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         16 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                       | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         17 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         18 | DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK                  | Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK  |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         19 | DEV_PRU_ICSSG2_BUS_CORE_CLK                                                         | Input muxed clock                                        |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         20 | DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         21 | DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         25 | DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK                                                  | Output clock                                             |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+
|         26 | DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK                                                  | Output clock                                             |
+------------+-------------------------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_psc0:


Clocks for PSC0 Device
----------------------

Device: :ref:`AM6_DEV_PSC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 70)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_PSC0_BUS_CLK      | Input clock |
+------------+-----------------------+-------------+
|          1 | DEV_PSC0_BUS_SLOW_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_psramecc0:


Clocks for PSRAMECC0 Device
---------------------------

Device: :ref:`AM6_DEV_PSRAMECC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 128)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_PSRAMECC0_BUS_CLK_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_rti0:


Clocks for RTI0 Device
----------------------

Device: :ref:`AM6_DEV_RTI0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 130)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                       | Function                                          |
+============+============================================================================+===================================================+
|          0 | DEV_RTI0_BUS_RTI_CLK                                                       | Input muxed clock                                 |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                    | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          7 | DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                    | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          8 | DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                    | Parent input clock option to DEV_RTI0_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          9 | DEV_RTI0_BUS_VBUSP_CLK                                                     | Input clock                                       |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_rti1:


Clocks for RTI1 Device
----------------------

Device: :ref:`AM6_DEV_RTI1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 131)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                       | Function                                          |
+============+============================================================================+===================================================+
|          0 | DEV_RTI1_BUS_RTI_CLK                                                       | Input muxed clock                                 |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                    | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          7 | DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                    | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          8 | DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                    | Parent input clock option to DEV_RTI1_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          9 | DEV_RTI1_BUS_VBUSP_CLK                                                     | Input clock                                       |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_rti2:


Clocks for RTI2 Device
----------------------

Device: :ref:`AM6_DEV_RTI2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 132)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                       | Function                                          |
+============+============================================================================+===================================================+
|          0 | DEV_RTI2_BUS_RTI_CLK                                                       | Input muxed clock                                 |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                    | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          7 | DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                    | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          8 | DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                    | Parent input clock option to DEV_RTI2_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          9 | DEV_RTI2_BUS_VBUSP_CLK                                                     | Input clock                                       |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_rti3:


Clocks for RTI3 Device
----------------------

Device: :ref:`AM6_DEV_RTI3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 133)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                       | Function                                          |
+============+============================================================================+===================================================+
|          0 | DEV_RTI3_BUS_RTI_CLK                                                       | Input muxed clock                                 |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK        | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                    | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                    | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          7 | DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                    | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          8 | DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                    | Parent input clock option to DEV_RTI3_BUS_RTI_CLK |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+
|          9 | DEV_RTI3_BUS_VBUSP_CLK                                                     | Input clock                                       |
+------------+----------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_sa2_ul0:


Clocks for SA2_UL0 Device
-------------------------

Device: :ref:`AM6_DEV_SA2_UL0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 136)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_SA2_UL0_BUS_PKA_IN_CLK | Input clock |
+------------+----------------------------+-------------+
|          1 | DEV_SA2_UL0_BUS_X1_CLK     | Input clock |
+------------+----------------------------+-------------+
|          2 | DEV_SA2_UL0_BUS_X2_CLK     | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_serdes0:


Clocks for SERDES0 Device
-------------------------

Device: :ref:`AM6_DEV_SERDES0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 153)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                              | Function                                               |
+============+===================================================================================+========================================================+
|          0 | DEV_SERDES0_BUS_IP3_LN0_TXRCLK                                                    | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_SERDES0_BUS_CLK                                                               | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_SERDES0_BUS_IP2_LN0_TXRCLK                                                    | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_SERDES0_BUS_LI_REFCLK                                                         | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK        | Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_SERDES0_BUS_LN0_TXCLK                                                         | Output clock                                           |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_SERDES0_BUS_LN0_RXCLK                                                         | Output clock                                           |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_serdes1:


Clocks for SERDES1 Device
-------------------------

Device: :ref:`AM6_DEV_SERDES1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 154)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                              | Function                                               |
+============+===================================================================================+========================================================+
|          0 | DEV_SERDES1_BUS_IP3_LN0_TXRCLK                                                    | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_SERDES1_BUS_CLK                                                               | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_SERDES1_BUS_IP1_LN0_TXRCLK                                                    | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_SERDES1_BUS_IP2_LN0_TXRCLK                                                    | Input clock                                            |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_SERDES1_BUS_RI_REFCLK                                                         | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK        | Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK | Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_SERDES1_BUS_LN0_TXCLK                                                         | Output clock                                           |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_SERDES1_BUS_LN0_RXCLK                                                         | Output clock                                           |
+------------+-----------------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_stm0:


Clocks for STM0 Device
----------------------

Device: :ref:`AM6_DEV_STM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 8)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_STM0_BUS_CORE_CLK  | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_STM0_BUS_ATB_CLK   | Input clock |
+------------+------------------------+-------------+
|          2 | DEV_STM0_BUS_VBUSP_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_timer0:


Clocks for TIMER0 Device
------------------------

Device: :ref:`AM6_DEV_TIMER0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 23)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER0_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER0_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer1:


Clocks for TIMER1 Device
------------------------

Device: :ref:`AM6_DEV_TIMER1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 24)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER1_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER1_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer10:


Clocks for TIMER10 Device
-------------------------

Device: :ref:`AM6_DEV_TIMER10 <soc_doc_am6_public_devices_desc_device_list>` (ID = 25)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|   Clock ID | Name                                                                                   | Function                                                    |
+============+========================================================================================+=============================================================+
|          0 | DEV_TIMER10_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                           |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          1 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          2 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          3 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          4 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          5 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          6 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          7 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          8 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          9 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         10 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         11 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         12 | DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         17 | DEV_TIMER10_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                 |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer11:


Clocks for TIMER11 Device
-------------------------

Device: :ref:`AM6_DEV_TIMER11 <soc_doc_am6_public_devices_desc_device_list>` (ID = 26)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|   Clock ID | Name                                                                                   | Function                                                    |
+============+========================================================================================+=============================================================+
|          0 | DEV_TIMER11_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                           |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          1 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          2 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          3 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          4 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          5 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          6 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          7 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          8 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|          9 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         10 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         11 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         12 | DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+
|         17 | DEV_TIMER11_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                 |
+------------+----------------------------------------------------------------------------------------+-------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer2:


Clocks for TIMER2 Device
------------------------

Device: :ref:`AM6_DEV_TIMER2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 27)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER2_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER2_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer3:


Clocks for TIMER3 Device
------------------------

Device: :ref:`AM6_DEV_TIMER3 <soc_doc_am6_public_devices_desc_device_list>` (ID = 28)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER3_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER3_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer4:


Clocks for TIMER4 Device
------------------------

Device: :ref:`AM6_DEV_TIMER4 <soc_doc_am6_public_devices_desc_device_list>` (ID = 29)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER4_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER4_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer5:


Clocks for TIMER5 Device
------------------------

Device: :ref:`AM6_DEV_TIMER5 <soc_doc_am6_public_devices_desc_device_list>` (ID = 30)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER5_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER5_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer6:


Clocks for TIMER6 Device
------------------------

Device: :ref:`AM6_DEV_TIMER6 <soc_doc_am6_public_devices_desc_device_list>` (ID = 31)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER6_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER6_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer7:


Clocks for TIMER7 Device
------------------------

Device: :ref:`AM6_DEV_TIMER7 <soc_doc_am6_public_devices_desc_device_list>` (ID = 32)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER7_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER7_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer8:


Clocks for TIMER8 Device
------------------------

Device: :ref:`AM6_DEV_TIMER8 <soc_doc_am6_public_devices_desc_device_list>` (ID = 33)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER8_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER8_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timer9:


Clocks for TIMER9 Device
------------------------

Device: :ref:`AM6_DEV_TIMER9 <soc_doc_am6_public_devices_desc_device_list>` (ID = 34)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                   |
+============+=======================================================================================+============================================================+
|          0 | DEV_TIMER9_BUS_TIMER_TCLK_CLK                                                         | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK          | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK    | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT                  | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT                      | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT                      | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT                     | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5             | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK     | Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_TIMER9_BUS_TIMER_HCLK_CLK                                                         | Input clock                                                |
+------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_timesync_intrtr0:


Clocks for TIMESYNC_INTRTR0 Device
----------------------------------

Device: :ref:`AM6_DEV_TIMESYNC_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 145)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_uart0:


Clocks for UART0 Device
-----------------------

Device: :ref:`AM6_DEV_UART0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 146)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_UART0_BUS_FCLK_CLK  | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_UART0_BUS_VBUSP_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_uart1:


Clocks for UART1 Device
-----------------------

Device: :ref:`AM6_DEV_UART1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 147)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_UART1_BUS_FCLK_CLK  | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_UART1_BUS_VBUSP_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_uart2:


Clocks for UART2 Device
-----------------------

Device: :ref:`AM6_DEV_UART2 <soc_doc_am6_public_devices_desc_device_list>` (ID = 148)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_UART2_BUS_FCLK_CLK  | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_UART2_BUS_VBUSP_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_usb3ss0:


Clocks for USB3SS0 Device
-------------------------

Device: :ref:`AM6_DEV_USB3SS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 151)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                                 | Function                                                   |
+============+======================================================================================+============================================================+
|          0 | DEV_USB3SS0_BUS_SUSP_CLK                                                             | Input clock                                                |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK                                                  | Input clock                                                |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_USB3SS0_BUS_REF_CLK                                                              | Input muxed clock                                          |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0                                    | Parent input clock option to DEV_USB3SS0_BUS_REF_CLK       |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48                 | Parent input clock option to DEV_USB3SS0_BUS_REF_CLK       |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_USB3SS0_BUS_HSIC_CLK_CLK                                                         | Input clock                                                |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_USB3SS0_BUS_BUS_CLK                                                              | Input clock                                                |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_USB3SS0_BUS_PIPE3_TXB_CLK                                                        | Input muxed clock                                          |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK                | Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_USB3SS0_BUS_UTMI_CLK_CLK                                                         | Input clock                                                |
+------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_usb3ss1:


Clocks for USB3SS1 Device
-------------------------

Device: :ref:`AM6_DEV_USB3SS1 <soc_doc_am6_public_devices_desc_device_list>` (ID = 152)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                             |
+============+======================================================================+======================================================+
|          0 | DEV_USB3SS1_BUS_SUSP_CLK                                             | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          1 | DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK                                  | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          2 | DEV_USB3SS1_BUS_REF_CLK                                              | Input muxed clock                                    |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          3 | DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0                    | Parent input clock option to DEV_USB3SS1_BUS_REF_CLK |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          4 | DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48 | Parent input clock option to DEV_USB3SS1_BUS_REF_CLK |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          5 | DEV_USB3SS1_BUS_HSIC_CLK_CLK                                         | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          6 | DEV_USB3SS1_BUS_BUS_CLK                                              | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          7 | DEV_USB3SS1_BUS_PIPE3_TXB_CLK                                        | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+
|          8 | DEV_USB3SS1_BUS_UTMI_CLK_CLK                                         | Input clock                                          |
+------------+----------------------------------------------------------------------+------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_vdc_data_vbusm_32b_ref_mcu2wkup:


Clocks for VDC_DATA_VBUSM_32B_REF_MCU2WKUP Device
-------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_data_vbusm_32b_ref_wkup2mcu:


Clocks for VDC_DATA_VBUSM_32B_REF_WKUP2MCU Device
-------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_data_vbusm_64b_ref_main2mcu:


Clocks for VDC_DATA_VBUSM_64B_REF_MAIN2MCU Device
-------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_data_vbusm_64b_ref_mcu2main:


Clocks for VDC_DATA_VBUSM_64B_REF_MCU2MAIN Device
-------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_dmsc_dbg_vbusp_32b_ref_dbg2dmsc:


Clocks for VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC Device
-----------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_infra_vbusp_32b_ref_mcu2main_infra:


Clocks for VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA Device
--------------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_infra_vbusp_32b_ref_wkup2main_infra:


Clocks for VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA Device
---------------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_mcu_dbg_vbusp_32b_ref_dbgmain2mcu:


Clocks for VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU Device
-------------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_nav_psil_128b_ref_main2mcu:


Clocks for VDC_NAV_PSIL_128B_REF_MAIN2MCU Device
------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_soc_fw_vbusp_32b_ref_fwmcu2main:


Clocks for VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN Device
-----------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_vdc_soc_fw_vbusp_32b_ref_fwwkup2mcu:


Clocks for VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU Device
-----------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_wkup_cbass0:


Clocks for WKUP_CBASS0 Device
-----------------------------

Device: :ref:`AM6_DEV_WKUP_CBASS0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 94)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------+-------------+
|   Clock ID | Name                                       | Function    |
+============+============================================+=============+
|          0 | DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK | Input clock |
+------------+--------------------------------------------+-------------+
|          1 | DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK | Input clock |
+------------+--------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_cbass_fw0:


Clocks for WKUP_CBASS_FW0 Device
--------------------------------

Device: :ref:`AM6_DEV_WKUP_CBASS_FW0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 96)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------+-------------+
|   Clock ID | Name                                          | Function    |
+============+===============================================+=============+
|          0 | DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK | Input clock |
+------------+-----------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_ctrl_mmr0:


Clocks for WKUP_CTRL_MMR0 Device
--------------------------------

Device: :ref:`AM6_DEV_WKUP_CTRL_MMR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 155)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_dmsc0:


Clocks for WKUP_DMSC0 Device
----------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_wkup_dmsc0_cortex_m3_0:


Clocks for WKUP_DMSC0_CORTEX_M3_0 Device
----------------------------------------

**This device has no defined clocks.**

.. _soc_doc_am65x_sr2_public_clks_wkup_ecc_aggr0:


Clocks for WKUP_ECC_AGGR0 Device
--------------------------------

Device: :ref:`AM6_DEV_WKUP_ECC_AGGR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 95)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------+-------------+
|   Clock ID | Name                            | Function    |
+============+=================================+=============+
|          0 | DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK | Input clock |
+------------+---------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_esm0:


Clocks for WKUP_ESM0 Device
---------------------------

Device: :ref:`AM6_DEV_WKUP_ESM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 54)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_WKUP_ESM0_BUS_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_gpio0:


Clocks for WKUP_GPIO0 Device
----------------------------

Device: :ref:`AM6_DEV_WKUP_GPIO0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 59)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                                  | Function                                                |
+============+=======================================================================================+=========================================================+
|          0 | DEV_WKUP_GPIO0_BUS_MMR_CLK                                                            | Input muxed clock                                       |
+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4      | Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK |
+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0 | Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK |
+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK        | Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK |
+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK      | Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK |
+------------+---------------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_gpiomux_intrtr0:


Clocks for WKUP_GPIOMUX_INTRTR0 Device
--------------------------------------

Device: :ref:`AM6_DEV_WKUP_GPIOMUX_INTRTR0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 156)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------+-------------+
|   Clock ID | Name                                  | Function    |
+============+=======================================+=============+
|          0 | DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK | Input clock |
+------------+---------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_i2c0:


Clocks for WKUP_I2C0 Device
---------------------------

Device: :ref:`AM6_DEV_WKUP_I2C0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 115)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                             | Function                                                 |
+============+==================================================================================+==========================================================+
|          0 | DEV_WKUP_I2C0_BUS_CLK                                                            | Input clock                                              |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_WKUP_I2C0_BUS_PISYS_CLK                                                      | Input muxed clock                                        |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK | Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK       | Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK |
+------------+----------------------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_pllctrl0:


Clocks for WKUP_PLLCTRL0 Device
-------------------------------

Device: :ref:`AM6_DEV_WKUP_PLLCTRL0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 77)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------+-------------+
|   Clock ID | Name                                      | Function    |
+============+===========================================+=============+
|          0 | DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK | Input clock |
+------------+-------------------------------------------+-------------+
|          1 | DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK      | Input clock |
+------------+-------------------------------------------+-------------+
|          2 | DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK      | Input clock |
+------------+-------------------------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_psc0:


Clocks for WKUP_PSC0 Device
---------------------------

Device: :ref:`AM6_DEV_WKUP_PSC0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 79)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_WKUP_PSC0_BUS_CLK      | Input clock |
+------------+----------------------------+-------------+
|          1 | DEV_WKUP_PSC0_BUS_SLOW_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_uart0:


Clocks for WKUP_UART0 Device
----------------------------

Device: :ref:`AM6_DEV_WKUP_UART0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 150)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                       | Function                                                 |
+============+============================================================================+==========================================================+
|          0 | DEV_WKUP_UART0_BUS_FCLK_CLK                                                | Input muxed clock                                        |
+------------+----------------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0              | Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK |
+------------+----------------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK | Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK |
+------------+----------------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_WKUP_UART0_BUS_VBUSP_CLK                                               | Input clock                                              |
+------------+----------------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_am65x_sr2_public_clks_wkup_vtm0:


Clocks for WKUP_VTM0 Device
---------------------------

Device: :ref:`AM6_DEV_WKUP_VTM0 <soc_doc_am6_public_devices_desc_device_list>` (ID = 80)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_WKUP_VTM0_BUS_FIX_REF_CLK | Input clock |
+------------+-------------------------------+-------------+
|          1 | DEV_WKUP_VTM0_BUS_VBUSP_CLK   | Input clock |
+------------+-------------------------------+-------------+

