================
AM6 PLL Defaults
================

.. _soc_doc_am65x_sr2_public_plls_desc_intro:


PLL Defaults for AM6 Device
===========================

This chapter provides information on the PLL defaults which the System firmware programs
for AM6 SoC.


This is what the system firmware programs after the PM board configuration is provided.
The exact M and N values programmed are based on the crystal connected on the board.
The crystal frequency is understood by the ROM from the BOOTPINS. This value is read
by the System Firmware from the DEVSTAT register to determine which HFOSC is connected to the device


The System Firmware maintains a table of device clock frequency defaults at which the PLLs
are programmed. This document is a reference that the users of System Firmware
can look at to determine the default PLL configuration done during boot when PM board configuration
message is sent.


Once the PM Init during board configuration is complete the bootloader or application can
program individual clocks of individual modules to tweak the clocks based on the usecase
which differ from the default. The APIs to refer to setting individual module clocks are
:ref:`pm_clocks_msg_set_freq`, :ref:`pm_clocks_msg_query_freq`.


The following table gives the PLL configurations for the input crystal Frequency of 19.2 MHz.

+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+======+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |     2 |  250 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |    12 | 1250 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |    12 | 1250 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |     8 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |     8 |  750 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |    12 |  625 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |    32 | 1925 |              0 |    1 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |     3 |  250 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |     3 |  250 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+

The following table gives the PLL configurations for the input crystal Frequency of 20.0 MHz.

+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+=====+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |     1 | 120 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |     1 | 100 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |     1 | 100 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |     8 | 768 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |     8 | 720 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |     8 | 400 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |     8 | 462 |              0 |    1 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |     1 |  80 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |     1 |  80 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+

The following table gives the PLL configurations for the input crystal Frequency of 24.0 MHz.

+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+======+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |     1 |  100 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |     3 |  250 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |    12 | 1000 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |    10 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |    10 |  750 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |    12 |  500 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |    24 | 1155 |              0 |    1 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |     3 |  200 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |     3 |  200 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+

The following table gives the PLL configurations for the input crystal Frequency of 25.0 MHz.

+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |   M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+=====+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |     1 |  96 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |     1 |  80 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |    10 | 800 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |    10 | 768 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |    10 | 720 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |    10 | 400 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |    10 | 462 |              0 |    1 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |     1 |  64 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |     1 |  64 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+-----+----------------+------+----------+----------+----------+----------+

The following table gives the PLL configurations for the input crystal Frequency of 26.0 MHz.

+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+======+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |    13 | 1200 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |    13 | 1000 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |    13 | 1000 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |    13 |  960 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |    13 |  900 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |    13 |  500 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |    26 | 1155 |              0 |    1 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |    13 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |    13 |  800 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+

The following table gives the PLL configurations for the input crystal Frequency of 27.0 MHz.

+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PLL Name                          |   CLKOUT Freq (Hz) |   N+1 |    M |   Fractional M |   M2 | HSDIV1   | HSDIV2   | HSDIV3   | HSDIV4   |
+===================================+====================+=======+======+================+======+==========+==========+==========+==========+
| MCU0 (ADPLLM_HSDIV_WRAP_MCU_0)    |          400000000 |     9 |  800 |              0 |    6 | 40       | 30       | 25       | 15       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| CPSW (ADPLLM_HSDIV_WRAP_MCU_1)    |          250000000 |    27 | 2000 |              0 |    8 | 10       | 10       | 15       | 6        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| MAIN (ADPLLLJM_HSDIV_WRAP_MAIN_0) |          100000000 |    27 | 2000 |              0 |   20 | 4        | 40       | 8        | 20       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER0 (ADPLLLJM_WRAP_MAIN_1)       |          960000000 |    18 | 1280 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| PER1 (ADPLLLJM_HSDIV_WRAP_MAIN_2) |          300000000 |    12 |  800 |              0 |    6 | 8        | 18       | 9        | 4        |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DDR (ADPLLLJM_WRAP_MAIN_3)        |          333333333 |    27 | 1000 |              0 |    3 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| DSS (ADPLLLJM_WRAP_MAIN_4)        |         1155000000 |    18 | 1540 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_6)          |          800000000 |    27 | 1600 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+
| ARM (ADPLLM_WRAP_MAIN_7)          |          800000000 |    27 | 1600 |              0 |    2 | NA       | NA       | NA       | NA       |
+-----------------------------------+--------------------+-------+------+----------------+------+----------+----------+----------+----------+

