=====================
AM6 Host Descriptions
=====================

.. _soc_doc_am6_public_host_desc_intro:

Introduction
============

This chapter provides information of Host IDs that are permitted in the am6
SoC. These host IDs represent processing entities (or PEs) which is mandatory
identification of a Host in a processor.

Typically a host is a 'compute entity' which may be an actual processor or even
a virtual machine. We just use host or processing entity to indicate the same
thing.

.. _soc_doc_am6_public_host_desc_host_list:

Enumeration of Host IDs
=======================

+-----------+-------------+-------------------+-----------------------------------------+
|   Host ID | Host Name   | Security Status   | Description                             |
+===========+=============+===================+=========================================+
|         0 | DMSC        | Secure            | Device Management and Security Control  |
+-----------+-------------+-------------------+-----------------------------------------+
|         3 | R5_0        | Non Secure        | Cortex R5 Context 0 on MCU island       |
+-----------+-------------+-------------------+-----------------------------------------+
|         4 | R5_1        | Secure            | Cortex R5 Context 1 on MCU island(Boot) |
+-----------+-------------+-------------------+-----------------------------------------+
|         5 | R5_2        | Non Secure        | Cortex R5 Context 2 on MCU island       |
+-----------+-------------+-------------------+-----------------------------------------+
|         6 | R5_3        | Secure            | Cortex R5 Context 3 on MCU island       |
+-----------+-------------+-------------------+-----------------------------------------+
|        10 | A53_0       | Secure            | Cortex A53 context 0 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        11 | A53_1       | Secure            | Cortex A53 context 1 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        12 | A53_2       | Non Secure        | Cortex A53 context 2 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        13 | A53_3       | Non Secure        | Cortex A53 context 3 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        14 | A53_4       | Non Secure        | Cortex A53 context 4 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        15 | A53_5       | Non Secure        | Cortex A53 context 5 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        16 | A53_6       | Non Secure        | Cortex A53 context 6 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        17 | A53_7       | Non Secure        | Cortex A53 context 7 on Main island     |
+-----------+-------------+-------------------+-----------------------------------------+
|        30 | GPU_0       | Non Secure        | SGX544 Context 0 on Main island         |
+-----------+-------------+-------------------+-----------------------------------------+
|        31 | GPU_1       | Non Secure        | SGX544 Context 1 on Main island         |
+-----------+-------------+-------------------+-----------------------------------------+
|        50 | ICSSG_0     | Non Secure        | ICSS Context 0 on Main island           |
+-----------+-------------+-------------------+-----------------------------------------+
|        51 | ICSSG_1     | Non Secure        | ICSS Context 1 on Main island           |
+-----------+-------------+-------------------+-----------------------------------------+
|        52 | ICSSG_2     | Non Secure        | ICSS Context 2 on Main island           |
+-----------+-------------+-------------------+-----------------------------------------+
|       128 | HOST_ID_ALL | N/A               | Host catch all.                         |
|           |             |                   | Used in board configuration resource    |
|           |             |                   | assignments to define resource ranges   |
|           |             |                   | useable by all hosts. Cannot be used    |
+-----------+-------------+-------------------+-----------------------------------------+


.. note::

   * Description provides an intended purpose
     of the host ID, though on some systems,
     this might be used differently, backing memory and
     link allocations are made with the specified purpose
     in mind
   * Security Status provides an intended purpose for the
     Host context
