=======================
J721E Clock Identifiers
=======================

.. _soc_doc_j721e_public_clks_desc_intro:


Clock for J721E Device
======================

This chapter provides information on clock IDs that identify clocks
incoming and outgoing from devices identified via
:ref:`device IDs <soc_doc_j721e_public_devices_desc_device_list>`
in J721E SoC.


TISCI message Power Management APIs define a device ID and clock ID as
parameters allowing a user to specify granular control of clocks
for a particular SoC subsystem.

.. _soc_doc_j721e_public_clks_dev_list:


Device wise clock ID list for J721E SoC
=======================================

This is an enumerated list of clocks per device ID that can be
controlled via the power management clock APIs

The following table describes functions implemented by clocks

+----------------------------------+---------------------------------------------------------------------------------------------+
| Function                         | Description                                                                                 |
+==================================+=============================================================================================+
| Input clock                      | Clock input to the SoC subsystem                                                            |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Output clock                     | Clock output from the SoC subsystem                                                         |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Input muxed clock                | Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source |
+----------------------------------+---------------------------------------------------------------------------------------------+
| Parent input clock option to XYZ | One of the parent clocks that can be used as a source clock to a input muxed clock          |
+----------------------------------+---------------------------------------------------------------------------------------------+

Also note: There are devices which do not have clock information.
These do have chapters in this document associated with them, however, these would be marked as:

**This device has no defined clocks.**

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

.. _soc_doc_j721e_public_clks_a72ss0:


Clocks for A72SS0 Device
------------------------

Device: :ref:`J721E_DEV_A72SS0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 4)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_A72SS0_CLUSTER_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_a72ss0_core0:


Clocks for A72SS0_CORE0 Device
------------------------------

Device: :ref:`J721E_DEV_A72SS0_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 202)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_A72SS0_CORE0_PLL_CTRL_CLK | Input clock |
+------------+-------------------------------+-------------+
|          1 | DEV_A72SS0_CORE0_MSMC_CLK     | Input clock |
+------------+-------------------------------+-------------+
|          2 | DEV_A72SS0_CORE0_ARM_CLK_CLK  | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_a72ss0_core1:


Clocks for A72SS0_CORE1 Device
------------------------------

Device: :ref:`J721E_DEV_A72SS0_CORE1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 203)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_A72SS0_CORE1_ARM_CLK_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_aasrc0:


Clocks for AASRC0 Device
------------------------

Device: :ref:`J721E_DEV_AASRC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 139)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------+----------------------------------------------------+
|   Clock ID | Name                                                            | Function                                           |
+============+=================================================================+====================================================+
|          0 | DEV_AASRC0_SYS_CLK                                              | Input clock                                        |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          1 | DEV_AASRC0_VBUSP_CLK                                            | Input clock                                        |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          2 | DEV_AASRC0_RX0_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          3 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          4 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          5 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          6 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          7 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          8 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|          9 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         10 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         11 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         12 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         13 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         14 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         15 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         16 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         17 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         18 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         19 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         20 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         21 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         22 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         23 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         24 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         25 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         26 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         27 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         28 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         29 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         30 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         31 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         32 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         33 | DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         34 | DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         35 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         36 | DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         37 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         38 | DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_RX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         39 | DEV_AASRC0_RX1_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         40 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         41 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         42 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         43 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         44 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         45 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         46 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         47 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         48 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         49 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         50 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         51 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         52 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         53 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         54 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         55 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         56 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         57 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         58 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         59 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         60 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         61 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         62 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         63 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         64 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         65 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         66 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         67 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         68 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         69 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         70 | DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         71 | DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         72 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         73 | DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         74 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         75 | DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_RX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         76 | DEV_AASRC0_RX2_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         77 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         78 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         79 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         80 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         81 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         82 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         83 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         84 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         85 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         86 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         87 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         88 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         89 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         90 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         91 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         92 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         93 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         94 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         95 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         96 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         97 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         98 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|         99 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        100 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        101 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        102 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        103 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        104 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        105 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        106 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        107 | DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        108 | DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        109 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        110 | DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        111 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        112 | DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_RX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        113 | DEV_AASRC0_RX3_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        114 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        115 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        116 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        117 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        118 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        119 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        120 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        121 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        122 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        123 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        124 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        125 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT           | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        126 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        127 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        128 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        129 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        130 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        131 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        132 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        133 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        134 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        135 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        136 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        137 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        138 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        139 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        140 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        141 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        142 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        143 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        144 | DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        145 | DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        146 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        147 | DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        148 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        149 | DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_RX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        150 | DEV_AASRC0_TX0_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        151 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        152 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        153 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        154 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        155 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        156 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        157 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        158 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        159 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        160 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        161 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        162 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        163 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        164 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        165 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        166 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        167 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        168 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        169 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        170 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        171 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        172 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        173 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        174 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        175 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        176 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        177 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        178 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        179 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        180 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        181 | DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        182 | DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        183 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        184 | DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        185 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        186 | DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_TX0_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        187 | DEV_AASRC0_TX1_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        188 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        189 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        190 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        191 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        192 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        193 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        194 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        195 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        196 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        197 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        198 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        199 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        200 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        201 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        202 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        203 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        204 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        205 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        206 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        207 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        208 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        209 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        210 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        211 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        212 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        213 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        214 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        215 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        216 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        217 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        218 | DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        219 | DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        220 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        221 | DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        222 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        223 | DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_TX1_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        224 | DEV_AASRC0_TX2_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        225 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        226 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        227 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        228 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        229 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        230 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        231 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        232 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        233 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        234 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        235 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        236 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        237 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        238 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        239 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        240 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        241 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        242 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        243 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        244 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        245 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        246 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        247 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        248 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        249 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        250 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        251 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        252 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        253 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        254 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        255 | DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        256 | DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        257 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        258 | DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        259 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        260 | DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_TX2_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        261 | DEV_AASRC0_TX3_SYNC_0                                           | Input muxed clock                                  |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        262 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        263 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        264 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        265 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        266 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        267 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        268 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        269 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        270 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        271 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        272 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        273 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT           | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        274 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        275 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        276 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        277 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        278 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        279 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        280 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        281 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        282 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        283 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0       | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        284 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        285 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0      | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        286 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        287 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        288 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        289 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        290 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        291 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        292 | DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK  | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        293 | DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        294 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0               | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        295 | DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1               | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        296 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT        | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+
|        297 | DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT            | Parent input clock option to DEV_AASRC0_TX3_SYNC_0 |
+------------+-----------------------------------------------------------------+----------------------------------------------------+

.. _soc_doc_j721e_public_clks_atl0:


Clocks for ATL0 Device
----------------------

Device: :ref:`J721E_DEV_ATL0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 2)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------+-----------------------------------------------+
|   Clock ID | Name                                                        | Function                                      |
+============+=============================================================+===============================================+
|          0 | DEV_ATL0_VBUS_CLK                                           | Input clock                                   |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          1 | DEV_ATL0_ATL_CLK                                            | Input muxed clock                             |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK   | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK   | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          4 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK  | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          5 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          6 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT         | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT             | Parent input clock option to DEV_ATL0_ATL_CLK |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          8 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1                            | Output clock                                  |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|          9 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0                            | Output clock                                  |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|         10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3                            | Output clock                                  |
+------------+-------------------------------------------------------------+-----------------------------------------------+
|         11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2                            | Output clock                                  |
+------------+-------------------------------------------------------------+-----------------------------------------------+

.. _soc_doc_j721e_public_clks_board0:


Clocks for BOARD0 Device
------------------------

Device: :ref:`J721E_DEV_BOARD0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 157)


.. note::


   BOARD0 is a special device that represents the board on which
   the SoC is mounted.

   Clocks that are incoming to or outgoing from the SoC are
   represented in this section from the *perspective of the board*.

   Function documented here implies:

   +----------------+---------------------------------------------------------------------------------------------+
   |    Function    | Description                                                                                 |
   +================+=============================================================================================+
   |  Input clock   | Clock is supplied from SoC to the board (It is an output of the SoC)                        |
   +----------------+---------------------------------------------------------------------------------------------+
   |  Output clock  | Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC) |
   +----------------+---------------------------------------------------------------------------------------------+

   **NOTE: Clocks which can be bi-directional are listed as Output clock**

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|   Clock ID | Name                                                                      | Function                                                     |
+============+===========================================================================+==============================================================+
|          0 | DEV_BOARD0_SPI0_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|          2 | DEV_BOARD0_SPI1_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|          4 | DEV_BOARD0_SPI2_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|          6 | DEV_BOARD0_SPI3_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|          8 | DEV_BOARD0_SPI5_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         10 | DEV_BOARD0_SPI6_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         12 | DEV_BOARD0_SPI7_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         14 | DEV_BOARD0_MCU_SPI0_CLK_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         16 | DEV_BOARD0_MCU_SPI1_CLK_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         18 | DEV_BOARD0_MCU_OSPI0_CLK_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         19 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN                                            | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         20 | DEV_BOARD0_MCU_OSPI0_DQS_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         21 | DEV_BOARD0_MCU_OSPI1_CLK_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         22 | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN                                            | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         23 | DEV_BOARD0_MCU_OSPI1_DQS_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         25 | DEV_BOARD0_I2C0_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         27 | DEV_BOARD0_I2C1_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         29 | DEV_BOARD0_I2C2_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         31 | DEV_BOARD0_I2C3_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         33 | DEV_BOARD0_I2C4_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         35 | DEV_BOARD0_I2C5_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         37 | DEV_BOARD0_I2C6_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         38 | DEV_BOARD0_MCU_I2C0_SCL_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         39 | DEV_BOARD0_MCU_I2C0_SCL_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         41 | DEV_BOARD0_MCU_I2C1_SCL_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         42 | DEV_BOARD0_WKUP_I2C0_SCL_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         43 | DEV_BOARD0_WKUP_I2C0_SCL_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         44 | DEV_BOARD0_I3C0_SCL_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         45 | DEV_BOARD0_I3C0_SCL_OUT                                                   | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         46 | DEV_BOARD0_MCU_I3C0_SCL_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         47 | DEV_BOARD0_MCU_I3C0_SCL_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         48 | DEV_BOARD0_MCU_I3C1_SCL_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         49 | DEV_BOARD0_MCU_I3C1_SCL_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         50 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN                                            | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         51 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN                                           | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         52 | DEV_BOARD0_DSI_TXCLKP_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         53 | DEV_BOARD0_DSI_TXCLKN_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         54 | DEV_BOARD0_PRG0_MDIO0_MDC_IN                                              | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         55 | DEV_BOARD0_PRG0_RGMII1_TXC_IN                                             | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         56 | DEV_BOARD0_PRG0_RGMII1_TXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         57 | DEV_BOARD0_PRG0_RGMII1_RXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         58 | DEV_BOARD0_PRG0_RGMII2_TXC_IN                                             | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         59 | DEV_BOARD0_PRG0_RGMII2_TXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         60 | DEV_BOARD0_PRG0_RGMII2_RXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         61 | DEV_BOARD0_PRG1_MDIO0_MDC_IN                                              | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         62 | DEV_BOARD0_PRG1_RGMII1_TXC_IN                                             | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         63 | DEV_BOARD0_PRG1_RGMII1_TXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         64 | DEV_BOARD0_PRG1_RGMII1_RXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         65 | DEV_BOARD0_PRG1_RGMII2_TXC_IN                                             | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         66 | DEV_BOARD0_PRG1_RGMII2_TXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         67 | DEV_BOARD0_PRG1_RGMII2_RXC_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         68 | DEV_BOARD0_MDIO0_MDC_IN                                                   | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         70 | DEV_BOARD0_RGMII3_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         72 | DEV_BOARD0_RGMII4_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         74 | DEV_BOARD0_RGMII5_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         76 | DEV_BOARD0_RGMII6_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         78 | DEV_BOARD0_RGMII7_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         80 | DEV_BOARD0_RGMII8_RXC_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         81 | DEV_BOARD0_RMII_REF_CLK_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         82 | DEV_BOARD0_CPTS0_RFT_CLK_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         83 | DEV_BOARD0_MCU_MDIO0_MDC_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         84 | DEV_BOARD0_MCU_RGMII1_TXC_IN                                              | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         85 | DEV_BOARD0_MCU_RGMII1_TXC_OUT                                             | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         86 | DEV_BOARD0_MCU_RGMII1_RXC_OUT                                             | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         87 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         88 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         89 | DEV_BOARD0_UFS0_REF_CLK_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         91 | DEV_BOARD0_DDR0_CK0_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         92 | DEV_BOARD0_DDR0_CK0_N_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|         99 | DEV_BOARD0_MMC0_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        100 | DEV_BOARD0_MMC1_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        101 | DEV_BOARD0_MMC2_CLK_IN                                                    | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        102 | DEV_BOARD0_GPMC0_CLK_IN                                                   | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        103 | DEV_BOARD0_GPMC0_CLK_OUT                                                  | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        104 | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                              | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        105 | DEV_BOARD0_MLB0_MLBCLK_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        106 | DEV_BOARD0_MLB0_MLBCP_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        108 | DEV_BOARD0_VPFE0_PCLK_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        109 | DEV_BOARD0_VOUT1_PCLK_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        110 | DEV_BOARD0_VOUT1_EXTPCLKIN_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        111 | DEV_BOARD0_VOUT2_PCLK_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        112 | DEV_BOARD0_VOUT2_EXTPCLKIN_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        113 | DEV_BOARD0_OBSCLK0_IN                                                     | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        114 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        115 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        116 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        117 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        118 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        119 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        120 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK            | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        126 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        127 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0                             | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        128 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        129 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        130 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        131 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        132 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        133 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        137 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        138 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        139 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK           | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        140 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0               | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        141 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK   | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        142 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        143 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0       | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        144 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                       | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        145 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | Parent input clock option to DEV_BOARD0_OBSCLK0_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        146 | DEV_BOARD0_OBSCLK1_IN                                                     | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        147 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4           | Parent input clock option to DEV_BOARD0_OBSCLK1_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        148 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8           | Parent input clock option to DEV_BOARD0_OBSCLK1_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        149 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4          | Parent input clock option to DEV_BOARD0_OBSCLK1_IN           |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        152 | DEV_BOARD0_MCU_OBSCLK0_IN                                                 | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        153 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                      | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN       |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        154 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                  | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN       |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        169 | DEV_BOARD0_SYSCLKOUT0_IN                                                  | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        170 | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                              | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        171 | DEV_BOARD0_TRC_CLK_IN                                                     | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        172 | DEV_BOARD0_CLKOUT_IN                                                      | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        173 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5            | Parent input clock option to DEV_BOARD0_CLKOUT_IN            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        174 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10           | Parent input clock option to DEV_BOARD0_CLKOUT_IN            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        175 | DEV_BOARD0_MCU_CLKOUT0_IN                                                 | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        176 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5        | Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN       |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        177 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10       | Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN       |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        178 | DEV_BOARD0_LED_CLK_OUT                                                    | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        179 | DEV_BOARD0_EXT_REFCLK1_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        180 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                            | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        181 | DEV_BOARD0_HFOSC1_CLK_OUT                                                 | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        182 | DEV_BOARD0_TCK_OUT                                                        | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        185 | DEV_BOARD0_PCIE_REFCLK0P_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        186 | DEV_BOARD0_PCIE_REFCLK0N_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        191 | DEV_BOARD0_PCIE_REFCLK1P_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        192 | DEV_BOARD0_PCIE_REFCLK1N_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        197 | DEV_BOARD0_PCIE_REFCLK2P_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        198 | DEV_BOARD0_PCIE_REFCLK2N_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        201 | DEV_BOARD0_PCIE_REFCLK3P_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        202 | DEV_BOARD0_PCIE_REFCLK3N_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        217 | DEV_BOARD0_MCASP0_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        218 | DEV_BOARD0_MCASP0_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        219 | DEV_BOARD0_MCASP0_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        220 | DEV_BOARD0_MCASP0_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        221 | DEV_BOARD0_MCASP0_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        222 | DEV_BOARD0_MCASP0_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        223 | DEV_BOARD0_MCASP1_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        224 | DEV_BOARD0_MCASP1_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        225 | DEV_BOARD0_MCASP1_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        226 | DEV_BOARD0_MCASP1_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        227 | DEV_BOARD0_MCASP1_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        228 | DEV_BOARD0_MCASP1_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        229 | DEV_BOARD0_MCASP2_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        230 | DEV_BOARD0_MCASP2_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        231 | DEV_BOARD0_MCASP2_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        232 | DEV_BOARD0_MCASP2_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        233 | DEV_BOARD0_MCASP2_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        234 | DEV_BOARD0_MCASP2_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        235 | DEV_BOARD0_MCASP3_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        236 | DEV_BOARD0_MCASP3_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        237 | DEV_BOARD0_MCASP3_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        238 | DEV_BOARD0_MCASP3_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        239 | DEV_BOARD0_MCASP3_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        240 | DEV_BOARD0_MCASP3_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        241 | DEV_BOARD0_MCASP4_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        242 | DEV_BOARD0_MCASP4_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        243 | DEV_BOARD0_MCASP4_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        244 | DEV_BOARD0_MCASP4_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        245 | DEV_BOARD0_MCASP4_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        246 | DEV_BOARD0_MCASP4_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        247 | DEV_BOARD0_MCASP5_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        248 | DEV_BOARD0_MCASP5_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        249 | DEV_BOARD0_MCASP5_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        250 | DEV_BOARD0_MCASP5_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        251 | DEV_BOARD0_MCASP5_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        252 | DEV_BOARD0_MCASP5_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        253 | DEV_BOARD0_MCASP6_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        254 | DEV_BOARD0_MCASP6_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        255 | DEV_BOARD0_MCASP6_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        256 | DEV_BOARD0_MCASP6_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        257 | DEV_BOARD0_MCASP6_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        258 | DEV_BOARD0_MCASP6_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        259 | DEV_BOARD0_MCASP7_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        260 | DEV_BOARD0_MCASP7_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        261 | DEV_BOARD0_MCASP7_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        262 | DEV_BOARD0_MCASP7_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        263 | DEV_BOARD0_MCASP7_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        264 | DEV_BOARD0_MCASP7_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        265 | DEV_BOARD0_MCASP8_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        267 | DEV_BOARD0_MCASP8_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        268 | DEV_BOARD0_MCASP8_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        269 | DEV_BOARD0_MCASP8_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        270 | DEV_BOARD0_MCASP8_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        271 | DEV_BOARD0_MCASP8_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        272 | DEV_BOARD0_MCASP9_ACLKR_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        273 | DEV_BOARD0_MCASP9_ACLKR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        274 | DEV_BOARD0_MCASP9_AFSR_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        275 | DEV_BOARD0_MCASP9_ACLKX_IN                                                | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        276 | DEV_BOARD0_MCASP9_ACLKX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        278 | DEV_BOARD0_MCASP9_AFSX_OUT                                                | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        279 | DEV_BOARD0_MCASP10_ACLKR_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        280 | DEV_BOARD0_MCASP10_ACLKR_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        281 | DEV_BOARD0_MCASP10_AFSR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        282 | DEV_BOARD0_MCASP10_ACLKX_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        283 | DEV_BOARD0_MCASP10_ACLKX_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        284 | DEV_BOARD0_MCASP10_AFSX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        285 | DEV_BOARD0_MCASP11_ACLKR_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        286 | DEV_BOARD0_MCASP11_ACLKR_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        287 | DEV_BOARD0_MCASP11_AFSR_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        288 | DEV_BOARD0_MCASP11_ACLKX_IN                                               | Input clock                                                  |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        289 | DEV_BOARD0_MCASP11_ACLKX_OUT                                              | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        290 | DEV_BOARD0_MCASP11_AFSX_OUT                                               | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        300 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        301 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                           | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        302 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        303 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        304 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        305 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        306 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        307 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        308 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        309 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        310 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        311 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        312 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        313 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        314 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        315 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        316 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        317 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        318 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        319 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        320 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        321 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        322 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        323 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        324 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        325 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        326 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        327 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        328 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        329 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        330 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        331 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        334 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT      | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        335 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        336 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                           | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        337 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        338 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        339 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        340 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        341 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        342 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        343 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        344 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        345 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        346 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        347 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        348 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        349 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        350 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        351 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        352 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        353 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        354 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        355 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        356 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        357 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        358 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        359 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        360 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        361 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        362 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        363 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        364 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        365 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        366 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        369 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT      | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        370 | DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        371 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN                                           | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        372 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        373 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        374 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        375 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        376 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        377 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        378 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        379 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        380 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        381 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        382 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        383 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        384 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        385 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        386 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        387 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        388 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        389 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        390 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        391 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        392 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        393 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        394 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        395 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        396 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        397 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        398 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        399 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        400 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        401 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        404 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT      | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        405 | DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT                                          | Output clock                                                 |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        406 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN                                           | Input muxed clock                                            |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        407 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        408 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        409 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        410 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        411 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        412 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        413 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        414 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        415 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        416 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        417 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        418 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        419 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        420 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        421 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        422 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        423 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        424 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        425 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        426 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        427 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        428 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0   | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        429 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        430 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        431 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        432 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        433 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        434 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        435 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK  | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        436 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+
|        439 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT      | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
+------------+---------------------------------------------------------------------------+--------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_c66ss0_core0:


Clocks for C66SS0_CORE0 Device
------------------------------

Device: :ref:`J721E_DEV_C66SS0_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 142)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+--------------+
|   Clock ID | Name                               | Function     |
+============+====================================+==============+
|          0 | DEV_C66SS0_CORE0_GEM_TRC_CLK       | Input clock  |
+------------+------------------------------------+--------------+
|          1 | DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK  | Output clock |
+------------+------------------------------------+--------------+
|          4 | DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK | Output clock |
+------------+------------------------------------+--------------+

.. _soc_doc_j721e_public_clks_c66ss0_introuter0:


Clocks for C66SS0_INTROUTER0 Device
-----------------------------------

Device: :ref:`J721E_DEV_C66SS0_INTROUTER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 121)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_C66SS0_INTROUTER0_INTR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_c66ss0_pbist0:


Clocks for C66SS0_PBIST0 Device
-------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_c66ss1_core0:


Clocks for C66SS1_CORE0 Device
------------------------------

Device: :ref:`J721E_DEV_C66SS1_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 143)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+--------------+
|   Clock ID | Name                               | Function     |
+============+====================================+==============+
|          0 | DEV_C66SS1_CORE0_GEM_TRC_CLK       | Input clock  |
+------------+------------------------------------+--------------+
|          1 | DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK  | Output clock |
+------------+------------------------------------+--------------+
|          4 | DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK | Output clock |
+------------+------------------------------------+--------------+

.. _soc_doc_j721e_public_clks_c66ss1_introuter0:


Clocks for C66SS1_INTROUTER0 Device
-----------------------------------

Device: :ref:`J721E_DEV_C66SS1_INTROUTER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 122)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_C66SS1_INTROUTER0_INTR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_c66ss1_pbist0:


Clocks for C66SS1_PBIST0 Device
-------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_c71ss0:


Clocks for C71SS0 Device
------------------------

Device: :ref:`J721E_DEV_C71SS0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 15)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_C71SS0_C7X_CLK      | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_C71SS0_PLL_CTRL_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_c71ss0_mma:


Clocks for C71SS0_MMA Device
----------------------------

Device: :ref:`J721E_DEV_C71SS0_MMA <soc_doc_j721e_public_devices_desc_device_list>` (ID = 16)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_C71SS0_MMA_PLL_CTRL_CLK | Input clock |
+------------+-----------------------------+-------------+
|          1 | DEV_C71SS0_MMA_MMA_CLK      | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_j721e_public_clks_c71x_0_pbist_vd:


Clocks for C71X_0_PBIST_VD Device
---------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_cmpevent_intrtr0:


Clocks for CMPEVENT_INTRTR0 Device
----------------------------------

Device: :ref:`J721E_DEV_CMPEVENT_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 123)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_cfg_wrap:


Clocks for COMPUTE_CLUSTER0_CFG_WRAP Device
-------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP <soc_doc_j721e_public_devices_desc_device_list>` (ID = 5)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_clec:


Clocks for COMPUTE_CLUSTER0_CLEC Device
---------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_CLEC <soc_doc_j721e_public_devices_desc_device_list>` (ID = 6)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK | Input clock |
+------------+------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_core_core:


Clocks for COMPUTE_CLUSTER0_CORE_CORE Device
--------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE <soc_doc_j721e_public_devices_desc_device_list>` (ID = 7)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------+-------------+
|   Clock ID | Name                                         | Function    |
+============+==============================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK | Input clock |
+------------+----------------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK      | Input clock |
+------------+----------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_ddr32ss_emif0_ew:


Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW Device
---------------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW <soc_doc_j721e_public_devices_desc_device_list>` (ID = 8)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------+-------------+
|   Clock ID | Name                                                    | Function    |
+============+=========================================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK      | Input clock |
+------------+---------------------------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK | Input clock |
+------------+---------------------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_debug_wrap:


Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP Device
---------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP <soc_doc_j721e_public_devices_desc_device_list>` (ID = 9)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------+-------------+
|   Clock ID | Name                                         | Function    |
+============+==============================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK | Input clock |
+------------+----------------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK | Input clock |
+------------+----------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_dmsc_wrap:


Clocks for COMPUTE_CLUSTER0_DMSC_WRAP Device
--------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP <soc_doc_j721e_public_devices_desc_device_list>` (ID = 12)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------+-------------+
|   Clock ID | Name                                        | Function    |
+============+=============================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK | Input clock |
+------------+---------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_en_msmc_domain:


Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN Device
-------------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN <soc_doc_j721e_public_devices_desc_device_list>` (ID = 13)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------+-------------+
|   Clock ID | Name                                              | Function    |
+============+===================================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK | Input clock |
+------------+---------------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_gic500ss:


Clocks for COMPUTE_CLUSTER0_GIC500SS Device
-------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_GIC500SS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 14)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster0_pbist_wrap:


Clocks for COMPUTE_CLUSTER0_PBIST_WRAP Device
---------------------------------------------

Device: :ref:`J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP <soc_doc_j721e_public_devices_desc_device_list>` (ID = 17)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------+-------------+
|   Clock ID | Name                                              | Function    |
+============+===================================================+=============+
|          0 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK | Input clock |
+------------+---------------------------------------------------+-------------+
|          1 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | Input clock |
+------------+---------------------------------------------------+-------------+
|          2 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK | Input clock |
+------------+---------------------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_compute_cluster_j7es_tb_vdc_main_0:


Clocks for COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 Device
----------------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_cpsw0:


Clocks for CPSW0 Device
-----------------------

Device: :ref:`J721E_DEV_CPSW0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 19)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                            |
+============+=========================================================================+=====================================================+
|          0 | DEV_CPSW0_GMII3_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_CPSW0_SERDES6_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_CPSW0_SERDES8_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_CPSW0_GMII2_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_CPSW0_SERDES2_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_CPSW0_SERDES4_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_CPSW0_SERDES7_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_CPSW0_SERDES7_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_CPSW0_SERDES6_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          9 | DEV_CPSW0_SERDES5_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         10 | DEV_CPSW0_SERDES5_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         11 | DEV_CPSW0_GMII4_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         12 | DEV_CPSW0_SERDES3_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         13 | DEV_CPSW0_SERDES2_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         14 | DEV_CPSW0_SERDES4_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         15 | DEV_CPSW0_SERDES6_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         16 | DEV_CPSW0_CPTS_RFT_CLK                                                  | Input muxed clock                                   |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         26 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         27 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         28 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         29 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK         | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         32 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         33 | DEV_CPSW0_SERDES5_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         34 | DEV_CPSW0_SERDES5_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         35 | DEV_CPSW0_GMII5_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         36 | DEV_CPSW0_SERDES2_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         37 | DEV_CPSW0_SERDES8_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         38 | DEV_CPSW0_SERDES1_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         39 | DEV_CPSW0_SERDES8_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         40 | DEV_CPSW0_GMII_RFT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         41 | DEV_CPSW0_SERDES3_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         42 | DEV_CPSW0_RGMII_MHZ_250_CLK                                             | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         43 | DEV_CPSW0_SERDES7_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         44 | DEV_CPSW0_GMII6_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         45 | DEV_CPSW0_SERDES6_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         46 | DEV_CPSW0_RMII_MHZ_50_CLK                                               | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         47 | DEV_CPSW0_GMII4_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         48 | DEV_CPSW0_SERDES2_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         49 | DEV_CPSW0_RGMII_MHZ_50_CLK                                              | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         50 | DEV_CPSW0_SERDES4_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         51 | DEV_CPSW0_SERDES3_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         52 | DEV_CPSW0_GMII8_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         53 | DEV_CPSW0_SERDES7_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         54 | DEV_CPSW0_GMII7_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         55 | DEV_CPSW0_GMII7_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         56 | DEV_CPSW0_SERDES6_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         57 | DEV_CPSW0_SERDES3_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         58 | DEV_CPSW0_SERDES4_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         59 | DEV_CPSW0_SERDES1_RXCLK                                                 | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         60 | DEV_CPSW0_SERDES1_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         61 | DEV_CPSW0_GMII6_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         62 | DEV_CPSW0_SERDES1_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         63 | DEV_CPSW0_RGMII_MHZ_5_CLK                                               | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         64 | DEV_CPSW0_SERDES5_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         65 | DEV_CPSW0_GMII2_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         66 | DEV_CPSW0_SERDES8_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         67 | DEV_CPSW0_GMII8_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         68 | DEV_CPSW0_GMII1_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         69 | DEV_CPSW0_SERDES8_REFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         70 | DEV_CPSW0_SERDES3_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         71 | DEV_CPSW0_GMII3_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         72 | DEV_CPSW0_SERDES1_TXMCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         73 | DEV_CPSW0_SERDES7_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         74 | DEV_CPSW0_GMII5_MR_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         75 | DEV_CPSW0_GMII1_MT_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         76 | DEV_CPSW0_SERDES2_RXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         77 | DEV_CPSW0_SERDES4_TXFCLK                                                | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         78 | DEV_CPSW0_SERDES3_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         79 | DEV_CPSW0_CPTS_GENF0_0                                                  | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         80 | DEV_CPSW0_SERDES5_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         81 | DEV_CPSW0_SERDES6_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         82 | DEV_CPSW0_SERDES8_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         83 | DEV_CPSW0_SERDES1_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         84 | DEV_CPSW0_SERDES4_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         85 | DEV_CPSW0_SERDES2_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         86 | DEV_CPSW0_SERDES7_TXCLK                                                 | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         87 | DEV_CPSW0_MDIO_MDCLK_O_0                                                | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         89 | DEV_CPSW0_CPPI_CLK_CLK                                                  | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_j721e_public_clks_cpt2_aggr0:


Clocks for CPT2_AGGR0 Device
----------------------------

Device: :ref:`J721E_DEV_CPT2_AGGR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 20)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_CPT2_AGGR0_VCLK_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_cpt2_aggr1:


Clocks for CPT2_AGGR1 Device
----------------------------

Device: :ref:`J721E_DEV_CPT2_AGGR1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 21)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_CPT2_AGGR1_VCLK_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_cpt2_aggr2:


Clocks for CPT2_AGGR2 Device
----------------------------

Device: :ref:`J721E_DEV_CPT2_AGGR2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 23)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_CPT2_AGGR2_VCLK_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_csi_psilss0:


Clocks for CSI_PSILSS0 Device
-----------------------------

Device: :ref:`J721E_DEV_CSI_PSILSS0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 25)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_CSI_PSILSS0_MAIN_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_csi_rx_if0:


Clocks for CSI_RX_IF0 Device
----------------------------

Device: :ref:`J721E_DEV_CSI_RX_IF0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 26)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_CSI_RX_IF0_VBUS_CLK_CLK    | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK | Input clock |
+------------+--------------------------------+-------------+
|          2 | DEV_CSI_RX_IF0_MAIN_CLK_CLK    | Input clock |
+------------+--------------------------------+-------------+
|          3 | DEV_CSI_RX_IF0_VP_CLK_CLK      | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_csi_rx_if1:


Clocks for CSI_RX_IF1 Device
----------------------------

Device: :ref:`J721E_DEV_CSI_RX_IF1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 27)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_CSI_RX_IF1_VBUS_CLK_CLK    | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK | Input clock |
+------------+--------------------------------+-------------+
|          2 | DEV_CSI_RX_IF1_MAIN_CLK_CLK    | Input clock |
+------------+--------------------------------+-------------+
|          3 | DEV_CSI_RX_IF1_VP_CLK_CLK      | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_csi_tx_if0:


Clocks for CSI_TX_IF0 Device
----------------------------

Device: :ref:`J721E_DEV_CSI_TX_IF0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 28)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------+-------------+
|   Clock ID | Name                                   | Function    |
+============+========================================+=============+
|          0 | DEV_CSI_TX_IF0_ESC_CLK_CLK             | Input clock |
+------------+----------------------------------------+-------------+
|          1 | DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK | Input clock |
+------------+----------------------------------------+-------------+
|          2 | DEV_CSI_TX_IF0_VBUS_CLK_CLK            | Input clock |
+------------+----------------------------------------+-------------+
|          3 | DEV_CSI_TX_IF0_MAIN_CLK_CLK            | Input clock |
+------------+----------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc0:


Clocks for DCC0 Device
----------------------

Device: :ref:`J721E_DEV_DCC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 30)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC0_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC0_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC0_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC0_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC0_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC0_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC0_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC0_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC0_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC0_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC0_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC0_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC0_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc1:


Clocks for DCC1 Device
----------------------

Device: :ref:`J721E_DEV_DCC1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 31)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC1_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC1_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC1_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC1_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC1_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC1_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC1_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC1_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC1_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC1_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC1_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC1_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC1_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc10:


Clocks for DCC10 Device
-----------------------

Device: :ref:`J721E_DEV_DCC10 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 41)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_DCC10_DCC_INPUT10_CLK | Input clock |
+------------+---------------------------+-------------+
|          1 | DEV_DCC10_DCC_INPUT01_CLK | Input clock |
+------------+---------------------------+-------------+
|          2 | DEV_DCC10_DCC_CLKSRC2_CLK | Input clock |
+------------+---------------------------+-------------+
|          3 | DEV_DCC10_DCC_CLKSRC7_CLK | Input clock |
+------------+---------------------------+-------------+
|          4 | DEV_DCC10_DCC_CLKSRC0_CLK | Input clock |
+------------+---------------------------+-------------+
|          5 | DEV_DCC10_VBUS_CLK        | Input clock |
+------------+---------------------------+-------------+
|          6 | DEV_DCC10_DCC_CLKSRC4_CLK | Input clock |
+------------+---------------------------+-------------+
|          7 | DEV_DCC10_DCC_CLKSRC1_CLK | Input clock |
+------------+---------------------------+-------------+
|          8 | DEV_DCC10_DCC_CLKSRC3_CLK | Input clock |
+------------+---------------------------+-------------+
|          9 | DEV_DCC10_DCC_INPUT00_CLK | Input clock |
+------------+---------------------------+-------------+
|         10 | DEV_DCC10_DCC_CLKSRC5_CLK | Input clock |
+------------+---------------------------+-------------+
|         11 | DEV_DCC10_DCC_CLKSRC6_CLK | Input clock |
+------------+---------------------------+-------------+
|         12 | DEV_DCC10_DCC_INPUT02_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc11:


Clocks for DCC11 Device
-----------------------

Device: :ref:`J721E_DEV_DCC11 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 42)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_DCC11_DCC_INPUT10_CLK | Input clock |
+------------+---------------------------+-------------+
|          1 | DEV_DCC11_DCC_INPUT01_CLK | Input clock |
+------------+---------------------------+-------------+
|          2 | DEV_DCC11_DCC_CLKSRC2_CLK | Input clock |
+------------+---------------------------+-------------+
|          3 | DEV_DCC11_DCC_CLKSRC7_CLK | Input clock |
+------------+---------------------------+-------------+
|          4 | DEV_DCC11_DCC_CLKSRC0_CLK | Input clock |
+------------+---------------------------+-------------+
|          5 | DEV_DCC11_VBUS_CLK        | Input clock |
+------------+---------------------------+-------------+
|          6 | DEV_DCC11_DCC_CLKSRC4_CLK | Input clock |
+------------+---------------------------+-------------+
|          7 | DEV_DCC11_DCC_CLKSRC1_CLK | Input clock |
+------------+---------------------------+-------------+
|          8 | DEV_DCC11_DCC_CLKSRC3_CLK | Input clock |
+------------+---------------------------+-------------+
|          9 | DEV_DCC11_DCC_INPUT00_CLK | Input clock |
+------------+---------------------------+-------------+
|         10 | DEV_DCC11_DCC_CLKSRC5_CLK | Input clock |
+------------+---------------------------+-------------+
|         11 | DEV_DCC11_DCC_CLKSRC6_CLK | Input clock |
+------------+---------------------------+-------------+
|         12 | DEV_DCC11_DCC_INPUT02_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc12:


Clocks for DCC12 Device
-----------------------

Device: :ref:`J721E_DEV_DCC12 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 43)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_DCC12_DCC_INPUT10_CLK | Input clock |
+------------+---------------------------+-------------+
|          1 | DEV_DCC12_DCC_INPUT01_CLK | Input clock |
+------------+---------------------------+-------------+
|          2 | DEV_DCC12_DCC_CLKSRC2_CLK | Input clock |
+------------+---------------------------+-------------+
|          3 | DEV_DCC12_DCC_CLKSRC7_CLK | Input clock |
+------------+---------------------------+-------------+
|          4 | DEV_DCC12_DCC_CLKSRC0_CLK | Input clock |
+------------+---------------------------+-------------+
|          5 | DEV_DCC12_VBUS_CLK        | Input clock |
+------------+---------------------------+-------------+
|          6 | DEV_DCC12_DCC_CLKSRC4_CLK | Input clock |
+------------+---------------------------+-------------+
|          7 | DEV_DCC12_DCC_CLKSRC1_CLK | Input clock |
+------------+---------------------------+-------------+
|          8 | DEV_DCC12_DCC_CLKSRC3_CLK | Input clock |
+------------+---------------------------+-------------+
|          9 | DEV_DCC12_DCC_INPUT00_CLK | Input clock |
+------------+---------------------------+-------------+
|         10 | DEV_DCC12_DCC_CLKSRC5_CLK | Input clock |
+------------+---------------------------+-------------+
|         11 | DEV_DCC12_DCC_CLKSRC6_CLK | Input clock |
+------------+---------------------------+-------------+
|         12 | DEV_DCC12_DCC_INPUT02_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc2:


Clocks for DCC2 Device
----------------------

Device: :ref:`J721E_DEV_DCC2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 32)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC2_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC2_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC2_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC2_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC2_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC2_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC2_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC2_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC2_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC2_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC2_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC2_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC2_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc3:


Clocks for DCC3 Device
----------------------

Device: :ref:`J721E_DEV_DCC3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 33)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC3_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC3_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC3_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC3_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC3_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC3_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC3_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC3_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC3_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC3_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC3_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC3_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC3_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc4:


Clocks for DCC4 Device
----------------------

Device: :ref:`J721E_DEV_DCC4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 34)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC4_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC4_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC4_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC4_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC4_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC4_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC4_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC4_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC4_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC4_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC4_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC4_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC4_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc5:


Clocks for DCC5 Device
----------------------

Device: :ref:`J721E_DEV_DCC5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 36)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC5_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC5_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC5_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC5_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC5_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC5_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC5_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC5_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC5_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC5_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC5_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC5_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC5_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc6:


Clocks for DCC6 Device
----------------------

Device: :ref:`J721E_DEV_DCC6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 37)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC6_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC6_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC6_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC6_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC6_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC6_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC6_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC6_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC6_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC6_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC6_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC6_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC6_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc7:


Clocks for DCC7 Device
----------------------

Device: :ref:`J721E_DEV_DCC7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 38)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC7_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC7_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC7_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC7_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC7_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC7_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC7_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC7_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC7_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC7_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC7_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC7_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC7_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc8:


Clocks for DCC8 Device
----------------------

Device: :ref:`J721E_DEV_DCC8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 39)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC8_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC8_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC8_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC8_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC8_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC8_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC8_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC8_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC8_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC8_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC8_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC8_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC8_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_dcc9:


Clocks for DCC9 Device
----------------------

Device: :ref:`J721E_DEV_DCC9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 40)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_DCC9_DCC_INPUT10_CLK | Input clock |
+------------+--------------------------+-------------+
|          1 | DEV_DCC9_DCC_INPUT01_CLK | Input clock |
+------------+--------------------------+-------------+
|          2 | DEV_DCC9_DCC_CLKSRC2_CLK | Input clock |
+------------+--------------------------+-------------+
|          3 | DEV_DCC9_DCC_CLKSRC7_CLK | Input clock |
+------------+--------------------------+-------------+
|          4 | DEV_DCC9_DCC_CLKSRC0_CLK | Input clock |
+------------+--------------------------+-------------+
|          5 | DEV_DCC9_VBUS_CLK        | Input clock |
+------------+--------------------------+-------------+
|          6 | DEV_DCC9_DCC_CLKSRC4_CLK | Input clock |
+------------+--------------------------+-------------+
|          7 | DEV_DCC9_DCC_CLKSRC1_CLK | Input clock |
+------------+--------------------------+-------------+
|          8 | DEV_DCC9_DCC_CLKSRC3_CLK | Input clock |
+------------+--------------------------+-------------+
|          9 | DEV_DCC9_DCC_INPUT00_CLK | Input clock |
+------------+--------------------------+-------------+
|         10 | DEV_DCC9_DCC_CLKSRC5_CLK | Input clock |
+------------+--------------------------+-------------+
|         11 | DEV_DCC9_DCC_CLKSRC6_CLK | Input clock |
+------------+--------------------------+-------------+
|         12 | DEV_DCC9_DCC_INPUT02_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_ddr0:


Clocks for DDR0 Device
----------------------

Device: :ref:`J721E_DEV_DDR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 47)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+--------------+
|   Clock ID | Name                       | Function     |
+============+============================+==============+
|          0 | DEV_DDR0_DDRSS_VBUS_CLK    | Input clock  |
+------------+----------------------------+--------------+
|          1 | DEV_DDR0_PLL_CTRL_CLK      | Input clock  |
+------------+----------------------------+--------------+
|          2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | Input clock  |
+------------+----------------------------+--------------+
|          3 | DEV_DDR0_DDRSS_CFG_CLK     | Input clock  |
+------------+----------------------------+--------------+
|          4 | DEV_DDR0_DDRSS_IO_CK_N_0   | Output clock |
+------------+----------------------------+--------------+
|          5 | DEV_DDR0_DDRSS_IO_CK_0     | Output clock |
+------------+----------------------------+--------------+

.. _soc_doc_j721e_public_clks_debugss_wrap0:


Clocks for DEBUGSS_WRAP0 Device
-------------------------------

Device: :ref:`J721E_DEV_DEBUGSS_WRAP0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 304)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------+--------------+
|   Clock ID | Name                                | Function     |
+============+=====================================+==============+
|          5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK        | Input clock  |
+------------+-------------------------------------+--------------+
|          9 | DEV_DEBUGSS_WRAP0_CORE_CLK          | Input clock  |
+------------+-------------------------------------+--------------+
|         25 | DEV_DEBUGSS_WRAP0_JTAG_TCK          | Input clock  |
+------------+-------------------------------------+--------------+
|         32 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0 | Output clock |
+------------+-------------------------------------+--------------+
|         35 | DEV_DEBUGSS_WRAP0_ATB_CLK           | Input clock  |
+------------+-------------------------------------+--------------+

.. _soc_doc_j721e_public_clks_decoder0:


Clocks for DECODER0 Device
--------------------------

Device: :ref:`J721E_DEV_DECODER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 144)

Following is a mapping of Clocks IDs to function:

+------------+----------------------+-------------+
|   Clock ID | Name                 | Function    |
+============+======================+=============+
|          0 | DEV_DECODER0_SYS_CLK | Input clock |
+------------+----------------------+-------------+

.. _soc_doc_j721e_public_clks_dmpac0_sde_0:


Clocks for DMPAC0_SDE_0 Device
------------------------------

Device: :ref:`J721E_DEV_DMPAC0_SDE_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 305)

Following is a mapping of Clocks IDs to function:

+------------+----------------------+-------------+
|   Clock ID | Name                 | Function    |
+============+======================+=============+
|          0 | DEV_DMPAC0_SDE_0_CLK | Input clock |
+------------+----------------------+-------------+

.. _soc_doc_j721e_public_clks_dmpac_top_main_0:


Clocks for DMPAC_TOP_MAIN_0 Device
----------------------------------

Device: :ref:`J721E_DEV_DMPAC_TOP_MAIN_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 48)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_DMPAC_TOP_MAIN_0_CLK         | Input clock |
+------------+----------------------------------+-------------+
|          1 | DEV_DMPAC_TOP_MAIN_0_PLL_DCO_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_dmsc_wkup_0:


Clocks for DMSC_WKUP_0 Device
-----------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_dphy_rx0:


Clocks for DPHY_RX0 Device
--------------------------

Device: :ref:`J721E_DEV_DPHY_RX0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 147)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+--------------+
|   Clock ID | Name                         | Function     |
+============+==============================+==============+
|          0 | DEV_DPHY_RX0_MAIN_CLK_CLK    | Input clock  |
+------------+------------------------------+--------------+
|          1 | DEV_DPHY_RX0_PPI_RX_BYTE_CLK | Output clock |
+------------+------------------------------+--------------+

.. _soc_doc_j721e_public_clks_dphy_rx1:


Clocks for DPHY_RX1 Device
--------------------------

Device: :ref:`J721E_DEV_DPHY_RX1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 148)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+--------------+
|   Clock ID | Name                         | Function     |
+============+==============================+==============+
|          0 | DEV_DPHY_RX1_MAIN_CLK_CLK    | Input clock  |
+------------+------------------------------+--------------+
|          1 | DEV_DPHY_RX1_PPI_RX_BYTE_CLK | Output clock |
+------------+------------------------------+--------------+

.. _soc_doc_j721e_public_clks_dphy_tx0:


Clocks for DPHY_TX0 Device
--------------------------

Device: :ref:`J721E_DEV_DPHY_TX0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 296)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_DPHY_TX0_CLK                                                   | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_DPHY_TX0_PSM_CLK                                               | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_DPHY_TX0_DPHY_REF_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                            | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_DPHY_TX0_CK_P_0                                                | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_DPHY_TX0_CK_M_0                                                | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                            | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_dss0:


Clocks for DSS0 Device
----------------------

Device: :ref:`J721E_DEV_DSS0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 152)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                        |
+============+==============================================================================+=================================================================+
|          0 | DEV_DSS0_DSS_FUNC_CLK                                                        | Input clock                                                     |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          1 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                           | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          4 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                           | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0               | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|          9 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                           | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         10 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         11 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         12 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         13 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                           | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         14 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         15 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         16 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         17 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0               | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         23 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                             | Output clock                                                    |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         24 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                          | Output clock                                                    |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         25 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                             | Output clock                                                    |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         27 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                             | Output clock                                                    |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                             | Output clock                                                    |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         31 | DEV_DSS0_DPI0_EXT_CLKSEL                                                     | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         32 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK           | Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL           |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         33 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT                  | Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL           |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         34 | DEV_DSS0_DPI1_EXT_CLKSEL                                                     | Input muxed clock                                               |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         35 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK           | Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL           |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+
|         36 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT                  | Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL           |
+------------+------------------------------------------------------------------------------+-----------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_dss_dsi0:


Clocks for DSS_DSI0 Device
--------------------------

Device: :ref:`J721E_DEV_DSS_DSI0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 150)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------+-------------+
|   Clock ID | Name                                  | Function    |
+============+=======================================+=============+
|          0 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK        | Input clock |
+------------+---------------------------------------+-------------+
|          1 | DEV_DSS_DSI0_DPI_0_CLK                | Input clock |
+------------+---------------------------------------+-------------+
|          2 | DEV_DSS_DSI0_PLL_CTRL_CLK             | Input clock |
+------------+---------------------------------------+-------------+
|          3 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | Input clock |
+------------+---------------------------------------+-------------+
|          4 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK        | Input clock |
+------------+---------------------------------------+-------------+
|          5 | DEV_DSS_DSI0_SYS_CLK                  | Input clock |
+------------+---------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_dss_edp0:


Clocks for DSS_EDP0 Device
--------------------------

Device: :ref:`J721E_DEV_DSS_EDP0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 151)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+--------------+
|   Clock ID | Name                        | Function     |
+============+=============================+==============+
|          0 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|          1 | DEV_DSS_EDP0_DPI_2_CLK      | Input clock  |
+------------+-----------------------------+--------------+
|          2 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|          3 | DEV_DSS_EDP0_PHY_LN0_RXCLK  | Input clock  |
+------------+-----------------------------+--------------+
|          4 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | Input clock  |
+------------+-----------------------------+--------------+
|          5 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|          6 | DEV_DSS_EDP0_PHY_LN0_REFCLK | Input clock  |
+------------+-----------------------------+--------------+
|          7 | DEV_DSS_EDP0_PHY_LN1_RXCLK  | Input clock  |
+------------+-----------------------------+--------------+
|          8 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|          9 | DEV_DSS_EDP0_DPI_4_CLK      | Input clock  |
+------------+-----------------------------+--------------+
|         10 | DEV_DSS_EDP0_DPI_2_2X_CLK   | Input clock  |
+------------+-----------------------------+--------------+
|         11 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         12 | DEV_DSS_EDP0_PHY_LN2_RXCLK  | Input clock  |
+------------+-----------------------------+--------------+
|         13 | DEV_DSS_EDP0_PHY_LN2_REFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         14 | DEV_DSS_EDP0_PHY_LN3_REFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         15 | DEV_DSS_EDP0_DPI_5_CLK      | Input clock  |
+------------+-----------------------------+--------------+
|         16 | DEV_DSS_EDP0_PHY_LN3_RXCLK  | Input clock  |
+------------+-----------------------------+--------------+
|         17 | DEV_DSS_EDP0_PHY_LN1_REFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         18 | DEV_DSS_EDP0_AIF_I2S_CLK    | Input clock  |
+------------+-----------------------------+--------------+
|         19 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         20 | DEV_DSS_EDP0_DPI_3_CLK      | Input clock  |
+------------+-----------------------------+--------------+
|         21 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         22 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | Input clock  |
+------------+-----------------------------+--------------+
|         23 | DEV_DSS_EDP0_PLL_CTRL_CLK   | Input clock  |
+------------+-----------------------------+--------------+
|         24 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | Input clock  |
+------------+-----------------------------+--------------+
|         25 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | Input clock  |
+------------+-----------------------------+--------------+
|         26 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | Input clock  |
+------------+-----------------------------+--------------+
|         27 | DEV_DSS_EDP0_PHY_LN2_TXCLK  | Output clock |
+------------+-----------------------------+--------------+
|         28 | DEV_DSS_EDP0_PHY_LN3_TXCLK  | Output clock |
+------------+-----------------------------+--------------+
|         29 | DEV_DSS_EDP0_PHY_LN0_TXCLK  | Output clock |
+------------+-----------------------------+--------------+
|         30 | DEV_DSS_EDP0_PHY_LN1_TXCLK  | Output clock |
+------------+-----------------------------+--------------+
|         36 | DEV_DSS_EDP0_DPTX_MOD_CLK   | Input clock  |
+------------+-----------------------------+--------------+

.. _soc_doc_j721e_public_clks_ecap0:


Clocks for ECAP0 Device
-----------------------

Device: :ref:`J721E_DEV_ECAP0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 80)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_ECAP0_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_ecap1:


Clocks for ECAP1 Device
-----------------------

Device: :ref:`J721E_DEV_ECAP1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 81)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_ECAP1_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_ecap2:


Clocks for ECAP2 Device
-----------------------

Device: :ref:`J721E_DEV_ECAP2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 82)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_ECAP2_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm0:


Clocks for EHRPWM0 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 83)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM0_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm1:


Clocks for EHRPWM1 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 84)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM1_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm2:


Clocks for EHRPWM2 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 85)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM2_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm3:


Clocks for EHRPWM3 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 86)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM3_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm4:


Clocks for EHRPWM4 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 87)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM4_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_ehrpwm5:


Clocks for EHRPWM5 Device
-------------------------

Device: :ref:`J721E_DEV_EHRPWM5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 88)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_EHRPWM5_VBUSP_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_elm0:


Clocks for ELM0 Device
----------------------

Device: :ref:`J721E_DEV_ELM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 89)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_ELM0_VBUSP_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_emif_data_0_vd:


Clocks for EMIF_DATA_0_VD Device
--------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_encoder0:


Clocks for ENCODER0 Device
--------------------------

Device: :ref:`J721E_DEV_ENCODER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 153)

Following is a mapping of Clocks IDs to function:

+------------+----------------------+-------------+
|   Clock ID | Name                 | Function    |
+============+======================+=============+
|          0 | DEV_ENCODER0_SYS_CLK | Input clock |
+------------+----------------------+-------------+

.. _soc_doc_j721e_public_clks_eqep0:


Clocks for EQEP0 Device
-----------------------

Device: :ref:`J721E_DEV_EQEP0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 94)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_EQEP0_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_eqep1:


Clocks for EQEP1 Device
-----------------------

Device: :ref:`J721E_DEV_EQEP1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 95)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_EQEP1_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_eqep2:


Clocks for EQEP2 Device
-----------------------

Device: :ref:`J721E_DEV_EQEP2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 96)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_EQEP2_VBUS_CLK | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_esm0:


Clocks for ESM0 Device
----------------------

Device: :ref:`J721E_DEV_ESM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 97)

Following is a mapping of Clocks IDs to function:

+------------+--------------+-------------+
|   Clock ID | Name         | Function    |
+============+==============+=============+
|          0 | DEV_ESM0_CLK | Input clock |
+------------+--------------+-------------+

.. _soc_doc_j721e_public_clks_fss_mcu_0:


Clocks for FSS_MCU_0 Device
---------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_gpio0:


Clocks for GPIO0 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 105)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO0_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio1:


Clocks for GPIO1 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 106)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO1_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio2:


Clocks for GPIO2 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 107)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO2_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio3:


Clocks for GPIO3 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 108)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO3_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio4:


Clocks for GPIO4 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 109)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO4_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio5:


Clocks for GPIO5 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 110)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO5_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio6:


Clocks for GPIO6 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 111)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO6_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpio7:


Clocks for GPIO7 Device
-----------------------

Device: :ref:`J721E_DEV_GPIO7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 112)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_GPIO7_MMR_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_gpiomux_intrtr0:


Clocks for GPIOMUX_INTRTR0 Device
---------------------------------

Device: :ref:`J721E_DEV_GPIOMUX_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 131)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_gpmc0:


Clocks for GPMC0 Device
-----------------------

Device: :ref:`J721E_DEV_GPMC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 115)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+-------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                        |
+============+======================================================================+=================================================+
|          0 | DEV_GPMC0_PI_GPMC_RET_CLK                                            | Input clock                                     |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          1 | DEV_GPMC0_VBUSP_CLK                                                  | Input clock                                     |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          2 | DEV_GPMC0_FUNC_CLK                                                   | Input muxed clock                               |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK          | Parent input clock option to DEV_GPMC0_FUNC_CLK |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          4 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6         | Parent input clock option to DEV_GPMC0_FUNC_CLK |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          5 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4         | Parent input clock option to DEV_GPMC0_FUNC_CLK |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          6 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | Parent input clock option to DEV_GPMC0_FUNC_CLK |
+------------+----------------------------------------------------------------------+-------------------------------------------------+
|          7 | DEV_GPMC0_PO_GPMC_DEV_CLK                                            | Output clock                                    |
+------------+----------------------------------------------------------------------+-------------------------------------------------+

.. _soc_doc_j721e_public_clks_gpu0_dft_pbist_0:


Clocks for GPU0_DFT_PBIST_0 Device
----------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_gpu0_gpucore_0:


Clocks for GPU0_GPUCORE_0 Device
--------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_gpu0_gpu_0:


Clocks for GPU0_GPU_0 Device
----------------------------

Device: :ref:`J721E_DEV_GPU0_GPU_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 125)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_GPU0_GPU_0_GPU_PLL_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_j721e_public_clks_gtc0:


Clocks for GTC0 Device
----------------------

Device: :ref:`J721E_DEV_GTC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 61)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------+-----------------------------------------------+
|   Clock ID | Name                                                              | Function                                      |
+============+===================================================================+===============================================+
|          0 | DEV_GTC0_VBUSP_CLK                                                | Input clock                                   |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          1 | DEV_GTC0_GTC_CLK                                                  | Input muxed clock                             |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|          9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         12 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         13 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         14 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         15 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK         | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+
|         17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_GTC0_GTC_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------+

.. _soc_doc_j721e_public_clks_i2c0:


Clocks for I2C0 Device
----------------------

Device: :ref:`J721E_DEV_I2C0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 187)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C0_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C0_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C0_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c1:


Clocks for I2C1 Device
----------------------

Device: :ref:`J721E_DEV_I2C1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 188)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C1_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C1_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C1_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c2:


Clocks for I2C2 Device
----------------------

Device: :ref:`J721E_DEV_I2C2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 189)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C2_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C2_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C2_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c3:


Clocks for I2C3 Device
----------------------

Device: :ref:`J721E_DEV_I2C3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 190)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C3_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C3_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C3_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c4:


Clocks for I2C4 Device
----------------------

Device: :ref:`J721E_DEV_I2C4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 191)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C4_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C4_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C4_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c5:


Clocks for I2C5 Device
----------------------

Device: :ref:`J721E_DEV_I2C5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 192)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C5_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C5_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C5_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i2c6:


Clocks for I2C6 Device
----------------------

Device: :ref:`J721E_DEV_I2C6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 193)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_I2C6_PISYS_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_I2C6_PISCL_0   | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_I2C6_CLK       | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_i3c0:


Clocks for I3C0 Device
----------------------

Device: :ref:`J721E_DEV_I3C0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 116)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+--------------+
|   Clock ID | Name                  | Function     |
+============+=======================+==============+
|          0 | DEV_I3C0_I3C_PCLK_CLK | Input clock  |
+------------+-----------------------+--------------+
|          1 | DEV_I3C0_I3C_SCL_DI   | Input clock  |
+------------+-----------------------+--------------+
|          2 | DEV_I3C0_I3C_SCLK_CLK | Input clock  |
+------------+-----------------------+--------------+
|          3 | DEV_I3C0_I3C_SCL_DO_0 | Output clock |
+------------+-----------------------+--------------+

.. _soc_doc_j721e_public_clks_j7_lascar_gpu_wrap_main_0:


Clocks for J7_LASCAR_GPU_WRAP_MAIN_0 Device
-------------------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_k3_c66_corepac_main_0:


Clocks for K3_C66_COREPAC_MAIN_0 Device
---------------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_k3_c66_corepac_main_1:


Clocks for K3_C66_COREPAC_MAIN_1 Device
---------------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_led0:


Clocks for LED0 Device
----------------------

Device: :ref:`J721E_DEV_LED0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 127)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_LED0_LED_CLK  | Input clock |
+------------+-------------------+-------------+
|          1 | DEV_LED0_VBUS_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_main2mcu_lvl_intrtr0:


Clocks for MAIN2MCU_LVL_INTRTR0 Device
--------------------------------------

Device: :ref:`J721E_DEV_MAIN2MCU_LVL_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 128)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_main2mcu_pls_intrtr0:


Clocks for MAIN2MCU_PLS_INTRTR0 Device
--------------------------------------

Device: :ref:`J721E_DEV_MAIN2MCU_PLS_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 130)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_main2wkupmcu_vd:


Clocks for MAIN2WKUPMCU_VD Device
---------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_mcan0:


Clocks for MCAN0 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 156)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN0_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN0_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan1:


Clocks for MCAN1 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 158)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN1_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN1_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan10:


Clocks for MCAN10 Device
------------------------

Device: :ref:`J721E_DEV_MCAN10 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 168)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                | Function                                                |
+============+=====================================================================+=========================================================+
|          0 | DEV_MCAN10_MCANSS_HCLK_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCAN10_MCANSS_CCLK_CLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan11:


Clocks for MCAN11 Device
------------------------

Device: :ref:`J721E_DEV_MCAN11 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 169)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                | Function                                                |
+============+=====================================================================+=========================================================+
|          0 | DEV_MCAN11_MCANSS_HCLK_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCAN11_MCANSS_CCLK_CLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan12:


Clocks for MCAN12 Device
------------------------

Device: :ref:`J721E_DEV_MCAN12 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 170)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                | Function                                                |
+============+=====================================================================+=========================================================+
|          0 | DEV_MCAN12_MCANSS_HCLK_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCAN12_MCANSS_CCLK_CLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan13:


Clocks for MCAN13 Device
------------------------

Device: :ref:`J721E_DEV_MCAN13 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 171)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                | Function                                                |
+============+=====================================================================+=========================================================+
|          0 | DEV_MCAN13_MCANSS_HCLK_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCAN13_MCANSS_CCLK_CLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
+------------+---------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan2:


Clocks for MCAN2 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 160)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN2_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN2_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan3:


Clocks for MCAN3 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 161)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN3_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN3_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan4:


Clocks for MCAN4 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 162)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN4_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN4_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan5:


Clocks for MCAN5 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 163)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN5_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN5_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan6:


Clocks for MCAN6 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 164)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN6_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN6_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan7:


Clocks for MCAN7 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 165)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN7_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN7_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan8:


Clocks for MCAN8 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 166)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN8_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN8_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcan9:


Clocks for MCAN9 Device
-----------------------

Device: :ref:`J721E_DEV_MCAN9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 167)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MCAN9_MCANSS_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCAN9_MCANSS_CCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT       | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp0:


Clocks for MCASP0 Device
------------------------

Device: :ref:`J721E_DEV_MCASP0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 174)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP0_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP0_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP0_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP0_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP0_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP0_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP0_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP0_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP0_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP0_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP0_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp1:


Clocks for MCASP1 Device
------------------------

Device: :ref:`J721E_DEV_MCASP1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 175)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP1_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP1_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP1_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP1_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP1_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP1_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP1_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP1_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP1_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP1_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP1_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp10:


Clocks for MCASP10 Device
-------------------------

Device: :ref:`J721E_DEV_MCASP10 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 184)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|   Clock ID | Name                                                                     | Function                                                    |
+============+==========================================================================+=============================================================+
|          0 | DEV_MCASP10_VBUSP_CLK                                                    | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          1 | DEV_MCASP10_AUX_CLK                                                      | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          2 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          3 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          4 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          6 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          7 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          8 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          9 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP10_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         10 | DEV_MCASP10_MCASP_ACLKX_POUT_0                                           | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         11 | DEV_MCASP10_MCASP_ACLKX_PIN_0                                            | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         12 | DEV_MCASP10_MCASP_ACLKR_POUT_0                                           | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         13 | DEV_MCASP10_MCASP_ACLKR_PIN_0                                            | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         14 | DEV_MCASP10_MCASP_AHCLKX_POUT_0                                          | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         15 | DEV_MCASP10_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         16 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         17 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         18 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         19 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         20 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         21 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         22 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         23 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         24 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         25 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         26 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         27 | DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         28 | DEV_MCASP10_MCASP_AHCLKR_POUT_0                                          | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         29 | DEV_MCASP10_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         30 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         31 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         32 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         33 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         34 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         35 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         36 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         37 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         38 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         39 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         40 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         41 | DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp11:


Clocks for MCASP11 Device
-------------------------

Device: :ref:`J721E_DEV_MCASP11 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 185)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|   Clock ID | Name                                                                     | Function                                                    |
+============+==========================================================================+=============================================================+
|          0 | DEV_MCASP11_VBUSP_CLK                                                    | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          1 | DEV_MCASP11_AUX_CLK                                                      | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          2 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          3 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          4 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          6 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          7 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          8 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|          9 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP11_AUX_CLK            |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         10 | DEV_MCASP11_MCASP_ACLKX_POUT_0                                           | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         11 | DEV_MCASP11_MCASP_ACLKX_PIN_0                                            | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         12 | DEV_MCASP11_MCASP_ACLKR_POUT_0                                           | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         13 | DEV_MCASP11_MCASP_ACLKR_PIN_0                                            | Input clock                                                 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         14 | DEV_MCASP11_MCASP_AHCLKX_POUT_0                                          | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         15 | DEV_MCASP11_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         16 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         17 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         18 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         19 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         20 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         21 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         22 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         23 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         24 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         25 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         26 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         27 | DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         28 | DEV_MCASP11_MCASP_AHCLKR_POUT_0                                          | Output clock                                                |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         29 | DEV_MCASP11_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                           |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         30 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         31 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         32 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         33 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         34 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         35 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         36 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         37 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         38 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         39 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         40 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+
|         41 | DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0 |
+------------+--------------------------------------------------------------------------+-------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp2:


Clocks for MCASP2 Device
------------------------

Device: :ref:`J721E_DEV_MCASP2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 176)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP2_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP2_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP2_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP2_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP2_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP2_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP2_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP2_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP2_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP2_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP2_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp3:


Clocks for MCASP3 Device
------------------------

Device: :ref:`J721E_DEV_MCASP3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 177)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP3_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP3_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP3_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP3_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP3_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP3_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP3_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP3_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP3_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP3_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP3_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp4:


Clocks for MCASP4 Device
------------------------

Device: :ref:`J721E_DEV_MCASP4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 178)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP4_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP4_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP4_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP4_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP4_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP4_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP4_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP4_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP4_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP4_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP4_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp5:


Clocks for MCASP5 Device
------------------------

Device: :ref:`J721E_DEV_MCASP5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 179)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP5_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP5_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP5_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP5_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP5_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP5_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP5_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP5_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP5_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP5_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP5_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp6:


Clocks for MCASP6 Device
------------------------

Device: :ref:`J721E_DEV_MCASP6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 180)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP6_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP6_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP6_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP6_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP6_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP6_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP6_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP6_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP6_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP6_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP6_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp7:


Clocks for MCASP7 Device
------------------------

Device: :ref:`J721E_DEV_MCASP7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 181)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP7_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP7_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP7_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP7_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP7_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP7_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP7_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP7_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP7_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP7_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP7_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp8:


Clocks for MCASP8 Device
------------------------

Device: :ref:`J721E_DEV_MCASP8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 182)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP8_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP8_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP8_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP8_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP8_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP8_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP8_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP8_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP8_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP8_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP8_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcasp9:


Clocks for MCASP9 Device
------------------------

Device: :ref:`J721E_DEV_MCASP9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 183)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_MCASP9_VBUSP_CLK                                                    | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCASP9_AUX_CLK                                                      | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK             | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK             | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK            | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0            | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1            | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2            | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3            | Parent input clock option to DEV_MCASP9_AUX_CLK            |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCASP9_MCASP_ACLKX_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_MCASP9_MCASP_ACLKX_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_MCASP9_MCASP_ACLKR_POUT_0                                           | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_MCASP9_MCASP_ACLKR_PIN_0                                            | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_MCASP9_MCASP_AHCLKX_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_MCASP9_MCASP_AHCLKX_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_MCASP9_MCASP_AHCLKR_POUT_0                                          | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_MCASP9_MCASP_AHCLKR_PIN_0                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3              | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT2            | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0 |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcspi0:


Clocks for MCSPI0 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 266)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI0_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI0_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI0_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi1:


Clocks for MCSPI1 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 267)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI1_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI1_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI1_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi2:


Clocks for MCSPI2 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 268)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI2_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI2_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI2_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi3:


Clocks for MCSPI3 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 269)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                       | Function                                               |
+============+============================================================+========================================================+
|          0 | DEV_MCSPI3_VBUSP_CLK                                       | Input clock                                            |
+------------+------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MCSPI3_CLKSPIREF_CLK                                   | Input clock                                            |
+------------+------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MCSPI3_IO_CLKSPII_CLK                                  | Input muxed clock                                      |
+------------+------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK |
+------------+------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MCSPI3_IO_CLKSPIO_CLK                                  | Output clock                                           |
+------------+------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcspi4:


Clocks for MCSPI4 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 270)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI4_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI4_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI4_IO_CLKSPII_CLK | Input clock  |
+------------+---------------------------+--------------+
|          3 | DEV_MCSPI4_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi5:


Clocks for MCSPI5 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 271)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI5_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI5_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI5_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi6:


Clocks for MCSPI6 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 272)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI6_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI6_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI6_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcspi7:


Clocks for MCSPI7 Device
------------------------

Device: :ref:`J721E_DEV_MCSPI7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 273)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCSPI7_VBUSP_CLK      | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCSPI7_CLKSPIREF_CLK  | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCSPI7_IO_CLKSPIO_CLK | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_adc0:


Clocks for MCU_ADC0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_ADC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 0)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                         | Function                                          |
+============+==============================================================+===================================================+
|          0 | DEV_MCU_ADC0_SYS_CLK                                         | Input clock                                       |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_MCU_ADC0_ADC_CLK                                         | Input muxed clock                                 |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT          | Parent input clock option to DEV_MCU_ADC0_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC0_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC0_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT      | Parent input clock option to DEV_MCU_ADC0_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_MCU_ADC0_VBUS_CLK                                        | Input clock                                       |
+------------+--------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_adc1:


Clocks for MCU_ADC1 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_ADC1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 1)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                         | Function                                          |
+============+==============================================================+===================================================+
|          0 | DEV_MCU_ADC1_SYS_CLK                                         | Input clock                                       |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_MCU_ADC1_ADC_CLK                                         | Input muxed clock                                 |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT          | Parent input clock option to DEV_MCU_ADC1_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC1_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC1_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT      | Parent input clock option to DEV_MCU_ADC1_ADC_CLK |
+------------+--------------------------------------------------------------+---------------------------------------------------+
|          6 | DEV_MCU_ADC1_VBUS_CLK                                        | Input clock                                       |
+------------+--------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_cpsw0:


Clocks for MCU_CPSW0 Device
---------------------------

Device: :ref:`J721E_DEV_MCU_CPSW0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 18)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_MCU_CPSW0_RGMII1_RXC_I                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK                                              | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_MCU_CPSW0_CPTS_RFT_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK        | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT              | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK          | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK           | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         19 | DEV_MCU_CPSW0_GMII_RFT_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         20 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK                                                | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         21 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK                                               | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         22 | DEV_MCU_CPSW0_CPPI_CLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         23 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK                                                | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         24 | DEV_MCU_CPSW0_GMII1_MR_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         25 | DEV_MCU_CPSW0_GMII1_MT_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         26 | DEV_MCU_CPSW0_RGMII1_TXC_I                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         27 | DEV_MCU_CPSW0_RGMII1_TXC_O                                                   | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         28 | DEV_MCU_CPSW0_CPTS_GENF0_0                                                   | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         29 | DEV_MCU_CPSW0_MDIO_MDCLK_O_0                                                 | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_cpt2_aggr0:


Clocks for MCU_CPT2_AGGR0 Device
--------------------------------

Device: :ref:`J721E_DEV_MCU_CPT2_AGGR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 24)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_dcc0:


Clocks for MCU_DCC0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_DCC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 44)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_MCU_DCC0_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_dcc1:


Clocks for MCU_DCC1 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_DCC1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 45)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_MCU_DCC1_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | Input clock |
+------------+------------------------------+-------------+
|         11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_dcc2:


Clocks for MCU_DCC2 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_DCC2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 46)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | Input clock |
+------------+------------------------------+-------------+
|          1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | Input clock |
+------------+------------------------------+-------------+
|          2 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | Input clock |
+------------+------------------------------+-------------+
|          3 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | Input clock |
+------------+------------------------------+-------------+
|          4 | DEV_MCU_DCC2_VBUS_CLK        | Input clock |
+------------+------------------------------+-------------+
|          5 | DEV_MCU_DCC2_DCC_CLKSRC4_CLK | Input clock |
+------------+------------------------------+-------------+
|          6 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | Input clock |
+------------+------------------------------+-------------+
|          7 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | Input clock |
+------------+------------------------------+-------------+
|          8 | DEV_MCU_DCC2_DCC_INPUT00_CLK | Input clock |
+------------+------------------------------+-------------+
|          9 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | Input clock |
+------------+------------------------------+-------------+
|         10 | DEV_MCU_DCC2_DCC_INPUT02_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_esm0:


Clocks for MCU_ESM0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_ESM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 98)

Following is a mapping of Clocks IDs to function:

+------------+------------------+-------------+
|   Clock ID | Name             | Function    |
+============+==================+=============+
|          0 | DEV_MCU_ESM0_CLK | Input clock |
+------------+------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_fss0_fsas_0:


Clocks for MCU_FSS0_FSAS_0 Device
---------------------------------

Device: :ref:`J721E_DEV_MCU_FSS0_FSAS_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 101)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_MCU_FSS0_FSAS_0_GCLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_fss0_hyperbus1p0_0:


Clocks for MCU_FSS0_HYPERBUS1P0_0 Device
----------------------------------------

Device: :ref:`J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 102)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------+--------------+
|   Clock ID | Name                                         | Function     |
+============+==============================================+==============+
|          0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | Input clock  |
+------------+----------------------------------------------+--------------+
|          1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | Input clock  |
+------------+----------------------------------------------+--------------+
|          2 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK           | Input clock  |
+------------+----------------------------------------------+--------------+
|          3 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK     | Input clock  |
+------------+----------------------------------------------+--------------+
|          4 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK     | Input clock  |
+------------+----------------------------------------------+--------------+
|          5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N     | Output clock |
+------------+----------------------------------------------+--------------+
|          6 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P     | Output clock |
+------------+----------------------------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_fss0_ospi_0:


Clocks for MCU_FSS0_OSPI_0 Device
---------------------------------

Device: :ref:`J721E_DEV_MCU_FSS0_OSPI_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 103)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                      | Function                                                       |
+============+===========================================================================+================================================================+
|          0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK                                         | Input muxed clock                                              |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK                                         | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK                                         | Input muxed clock                                              |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT        | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK   | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          7 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK                                         | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK                                          | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK                                         | Output clock                                                   |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_fss0_ospi_1:


Clocks for MCU_FSS0_OSPI_1 Device
---------------------------------

Device: :ref:`J721E_DEV_MCU_FSS0_OSPI_1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 104)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|   Clock ID | Name                                                                      | Function                                                       |
+============+===========================================================================+================================================================+
|          0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK                                         | Input muxed clock                                              |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          1 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          2 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          3 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK                                         | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          4 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK                                         | Input muxed clock                                              |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          5 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT        | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          6 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK   | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK                                         | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          8 | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK                                          | Input clock                                                    |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
|          9 | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK                                         | Output clock                                                   |
+------------+---------------------------------------------------------------------------+----------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_i2c0:


Clocks for MCU_I2C0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_I2C0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 194)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+--------------+
|   Clock ID | Name                   | Function     |
+============+========================+==============+
|          0 | DEV_MCU_I2C0_PISYS_CLK | Input clock  |
+------------+------------------------+--------------+
|          1 | DEV_MCU_I2C0_PISCL_0   | Input clock  |
+------------+------------------------+--------------+
|          2 | DEV_MCU_I2C0_CLK       | Input clock  |
+------------+------------------------+--------------+
|          3 | DEV_MCU_I2C0_PORSCL_0  | Output clock |
+------------+------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_i2c1:


Clocks for MCU_I2C1 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_I2C1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 195)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_MCU_I2C1_PISYS_CLK | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_MCU_I2C1_PISCL_0   | Input clock |
+------------+------------------------+-------------+
|          2 | DEV_MCU_I2C1_CLK       | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_i3c0:


Clocks for MCU_I3C0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_I3C0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 117)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCU_I3C0_I3C_PCLK_CLK | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCU_I3C0_I3C_SCL_DI   | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCU_I3C0_I3C_SCLK_CLK | Input clock  |
+------------+---------------------------+--------------+
|          3 | DEV_MCU_I3C0_I3C_SCL_DO_0 | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_i3c1:


Clocks for MCU_I3C1 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_I3C1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 118)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+--------------+
|   Clock ID | Name                      | Function     |
+============+===========================+==============+
|          0 | DEV_MCU_I3C1_I3C_PCLK_CLK | Input clock  |
+------------+---------------------------+--------------+
|          1 | DEV_MCU_I3C1_I3C_SCL_DI   | Input clock  |
+------------+---------------------------+--------------+
|          2 | DEV_MCU_I3C1_I3C_SCLK_CLK | Input clock  |
+------------+---------------------------+--------------+
|          3 | DEV_MCU_I3C1_I3C_SCL_DO_0 | Output clock |
+------------+---------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_mcan0:


Clocks for MCU_MCAN0 Device
---------------------------

Device: :ref:`J721E_DEV_MCU_MCAN0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 172)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT      | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT          | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_mcan1:


Clocks for MCU_MCAN1 Device
---------------------------

Device: :ref:`J721E_DEV_MCU_MCAN1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 173)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT      | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT          | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_mcspi0:


Clocks for MCU_MCSPI0 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_MCSPI0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 274)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCU_MCSPI0_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCU_MCSPI0_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_mcspi1:


Clocks for MCU_MCSPI1 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_MCSPI1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 275)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                           | Function                                                   |
+============+================================================================+============================================================+
|          0 | DEV_MCU_MCSPI1_VBUSP_CLK                                       | Input clock                                                |
+------------+----------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_MCSPI1_CLKSPIREF_CLK                                   | Input clock                                                |
+------------+----------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK                                  | Input muxed clock                                          |
+------------+----------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK |
+------------+----------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK                                  | Output clock                                               |
+------------+----------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_mcspi2:


Clocks for MCU_MCSPI2 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_MCSPI2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 276)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+--------------+
|   Clock ID | Name                          | Function     |
+============+===============================+==============+
|          0 | DEV_MCU_MCSPI2_VBUSP_CLK      | Input clock  |
+------------+-------------------------------+--------------+
|          1 | DEV_MCU_MCSPI2_CLKSPIREF_CLK  | Input clock  |
+------------+-------------------------------+--------------+
|          2 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | Input clock  |
+------------+-------------------------------+--------------+
|          3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | Output clock |
+------------+-------------------------------+--------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_intaggr_0:


Clocks for MCU_NAVSS0_INTAGGR_0 Device
--------------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_INTAGGR_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 233)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_NAVSS0_INTAGGR_0_SYS_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_intr_router_0:


Clocks for MCU_NAVSS0_INTR_ROUTER_0 Device
------------------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 237)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------+-------------+
|   Clock ID | Name                                  | Function    |
+============+=======================================+=============+
|          0 | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK | Input clock |
+------------+---------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_mcrc_0:


Clocks for MCU_NAVSS0_MCRC_0 Device
-----------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_MCRC_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 238)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_MCU_NAVSS0_MCRC_0_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_modss:


Clocks for MCU_NAVSS0_MODSS Device
----------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_MODSS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 302)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------+-------------+
|   Clock ID | Name                        | Function    |
+============+=============================+=============+
|          0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | Input clock |
+------------+-----------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_proxy_0:


Clocks for MCU_NAVSS0_PROXY_0 Device
------------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_PROXY_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 234)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_NAVSS0_PROXY_0_CLK_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_ringacc_0:


Clocks for MCU_NAVSS0_RINGACC_0 Device
--------------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_RINGACC_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 235)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------+-------------+
|   Clock ID | Name                             | Function    |
+============+==================================+=============+
|          0 | DEV_MCU_NAVSS0_RINGACC_0_SYS_CLK | Input clock |
+------------+----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_udmap_0:


Clocks for MCU_NAVSS0_UDMAP_0 Device
------------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_UDMAP_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 236)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_navss0_udmass:


Clocks for MCU_NAVSS0_UDMASS Device
-----------------------------------

Device: :ref:`J721E_DEV_MCU_NAVSS0_UDMASS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 303)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_pbist0:


Clocks for MCU_PBIST0 Device
----------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_mcu_pbist1:


Clocks for MCU_PBIST1 Device
----------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_mcu_r5fss0_core0:


Clocks for MCU_R5FSS0_CORE0 Device
----------------------------------

Device: :ref:`J721E_DEV_MCU_R5FSS0_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 250)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                                  |
+============+================================================================================+===========================================================+
|          0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK                                                   | Input muxed clock                                         |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK  | Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK                                             | Input clock                                               |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_r5fss0_core1:


Clocks for MCU_R5FSS0_CORE1 Device
----------------------------------

Device: :ref:`J721E_DEV_MCU_R5FSS0_CORE1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 251)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                           | Function                                                  |
+============+================================================================================+===========================================================+
|          0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK                                                   | Input muxed clock                                         |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK  | Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK                                             | Input clock                                               |
+------------+--------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_rti0:


Clocks for MCU_RTI0 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_RTI0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 262)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                          |
+============+========================================================================+===================================================+
|          0 | DEV_MCU_RTI0_VBUSP_CLK                                                 | Input clock                                       |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_MCU_RTI0_RTI_CLK                                                   | Input muxed clock                                 |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_rti1:


Clocks for MCU_RTI1 Device
--------------------------

Device: :ref:`J721E_DEV_MCU_RTI1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 263)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+---------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                          |
+============+========================================================================+===================================================+
|          0 | DEV_MCU_RTI1_VBUSP_CLK                                                 | Input clock                                       |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          1 | DEV_MCU_RTI1_RTI_CLK                                                   | Input muxed clock                                 |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          3 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+
|          5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
+------------+------------------------------------------------------------------------+---------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_sa2_ul0:


Clocks for MCU_SA2_UL0 Device
-----------------------------

Device: :ref:`J721E_DEV_MCU_SA2_UL0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 265)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_MCU_SA2_UL0_X2_CLK     | Input clock |
+------------+----------------------------+-------------+
|          1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | Input clock |
+------------+----------------------------+-------------+
|          2 | DEV_MCU_SA2_UL0_X1_CLK     | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_j721e_public_clks_mcu_timer0:


Clocks for MCU_TIMER0 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 35)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                   |
+============+=================================================================================+============================================================+
|          0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK                                                   | Input clock                                                |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK                                                   | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK           | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0              | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCU_TIMER0_TIMER_PWM_0                                                      | Output clock                                               |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer1:


Clocks for MCU_TIMER1 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 71)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1            | Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM_0 | Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer2:


Clocks for MCU_TIMER2 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 72)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                   |
+============+=================================================================================+============================================================+
|          0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK                                                   | Input clock                                                |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK                                                   | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK           | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0              | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCU_TIMER2_TIMER_PWM_0                                                      | Output clock                                               |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer3:


Clocks for MCU_TIMER3 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 73)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3            | Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM_0 | Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer4:


Clocks for MCU_TIMER4 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 74)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                   |
+============+=================================================================================+============================================================+
|          0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK                                                   | Input clock                                                |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK                                                   | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK           | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0              | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCU_TIMER4_TIMER_PWM_0                                                      | Output clock                                               |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer5:


Clocks for MCU_TIMER5 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 75)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5            | Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM_0 | Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer6:


Clocks for MCU_TIMER6 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 76)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                   |
+============+=================================================================================+============================================================+
|          0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK                                                   | Input clock                                                |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK                                                   | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK           | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0              | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCU_TIMER6_TIMER_PWM_0                                                      | Output clock                                               |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer7:


Clocks for MCU_TIMER7 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 77)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7            | Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM_0 | Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer8:


Clocks for MCU_TIMER8 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 78)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                            | Function                                                   |
+============+=================================================================================+============================================================+
|          0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK                                                   | Input clock                                                |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK                                                   | Input muxed clock                                          |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK           | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0              | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_MCU_TIMER8_TIMER_PWM_0                                                      | Output clock                                               |
+------------+---------------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_timer9:


Clocks for MCU_TIMER9 Device
----------------------------

Device: :ref:`J721E_DEV_MCU_TIMER9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 79)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                   |
+============+=======================================================================+============================================================+
|          0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK                                         | Input clock                                                |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK                                         | Input muxed clock                                          |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9            | Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM_0 | Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mcu_uart0:


Clocks for MCU_UART0 Device
---------------------------

Device: :ref:`J721E_DEV_MCU_UART0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 149)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                              | Function                                            |
+============+===================================================================+=====================================================+
|          0 | DEV_MCU_UART0_FCLK_CLK                                            | Input muxed clock                                   |
+------------+-------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK    | Parent input clock option to DEV_MCU_UART0_FCLK_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK | Parent input clock option to DEV_MCU_UART0_FCLK_CLK |
+------------+-------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_MCU_UART0_VBUSP_CLK                                           | Input clock                                         |
+------------+-------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_j721e_public_clks_mlb0:


Clocks for MLB0 Device
----------------------

Device: :ref:`J721E_DEV_MLB0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 186)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_MLB0_MLBSS_MLB_CLK  | Input clock |
+------------+-------------------------+-------------+
|          1 | DEV_MLB0_MLBSS_SCLK_CLK | Input clock |
+------------+-------------------------+-------------+
|          2 | DEV_MLB0_MLBSS_HCLK_CLK | Input clock |
+------------+-------------------------+-------------+
|          3 | DEV_MLB0_MLBSS_PCLK_CLK | Input clock |
+------------+-------------------------+-------------+
|          4 | DEV_MLB0_MLBSS_AMLB_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_mmcsd0:


Clocks for MMCSD0 Device
------------------------

Device: :ref:`J721E_DEV_MMCSD0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 91)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_MMCSD0_EMMCSS_VBUS_CLK                                         | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_MMCSD0_EMMCSS_XIN_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_MMCSD0_EMMCSS_IO_CLK_0                                         | Output clock                                           |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mmcsd1:


Clocks for MMCSD1 Device
------------------------

Device: :ref:`J721E_DEV_MMCSD1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 92)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                 |
+============+======================================================================+==========================================================+
|          0 | DEV_MMCSD1_EMMCSDSS_XIN_CLK                                          | Input muxed clock                                        |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          5 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK                                         | Input clock                                              |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          6 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I_0                                       | Input clock                                              |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O_0                                       | Output clock                                             |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_mmcsd2:


Clocks for MMCSD2 Device
------------------------

Device: :ref:`J721E_DEV_MMCSD2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 93)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                 |
+============+======================================================================+==========================================================+
|          0 | DEV_MMCSD2_EMMCSDSS_XIN_CLK                                          | Input muxed clock                                        |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          1 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          2 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          3 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          4 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          5 | DEV_MMCSD2_EMMCSDSS_VBUS_CLK                                         | Input clock                                              |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          6 | DEV_MMCSD2_EMMCSDSS_IO_CLK_I_0                                       | Input clock                                              |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+
|          7 | DEV_MMCSD2_EMMCSDSS_IO_CLK_O_0                                       | Output clock                                             |
+------------+----------------------------------------------------------------------+----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_navss0_cpts_0:


Clocks for NAVSS0_CPTS_0 Device
-------------------------------

Device: :ref:`J721E_DEV_NAVSS0_CPTS_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 201)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                            |
+============+=========================================================================+=====================================================+
|          0 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK                                            | Input clock                                         |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          1 | DEV_NAVSS0_CPTS_0_RCLK                                                  | Input muxed clock                                   |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|          9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         12 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         13 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         14 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         15 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK         | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         17 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         18 | DEV_NAVSS0_CPTS_0_TS_GENF0                                              | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+
|         19 | DEV_NAVSS0_CPTS_0_TS_GENF1                                              | Output clock                                        |
+------------+-------------------------------------------------------------------------+-----------------------------------------------------+

.. _soc_doc_j721e_public_clks_navss0_dti_0:


Clocks for NAVSS0_DTI_0 Device
------------------------------

Device: :ref:`J721E_DEV_NAVSS0_DTI_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 206)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_NAVSS0_DTI_0_CLK_CLK          | Input clock |
+------------+-----------------------------------+-------------+
|          1 | DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK | Input clock |
+------------+-----------------------------------+-------------+
|          2 | DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK | Input clock |
+------------+-----------------------------------+-------------+
|          3 | DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK | Input clock |
+------------+-----------------------------------+-------------+
|          4 | DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_intr_router_0:


Clocks for NAVSS0_INTR_ROUTER_0 Device
--------------------------------------

Device: :ref:`J721E_DEV_NAVSS0_INTR_ROUTER_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 213)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_0:


Clocks for NAVSS0_MAILBOX_0 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 214)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_1:


Clocks for NAVSS0_MAILBOX_1 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 215)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_10:


Clocks for NAVSS0_MAILBOX_10 Device
-----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_10 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 224)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_11:


Clocks for NAVSS0_MAILBOX_11 Device
-----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_11 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 225)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_2:


Clocks for NAVSS0_MAILBOX_2 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 216)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_3:


Clocks for NAVSS0_MAILBOX_3 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 217)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_4:


Clocks for NAVSS0_MAILBOX_4 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 218)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_5:


Clocks for NAVSS0_MAILBOX_5 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 219)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_6:


Clocks for NAVSS0_MAILBOX_6 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 220)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_7:


Clocks for NAVSS0_MAILBOX_7 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 221)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_8:


Clocks for NAVSS0_MAILBOX_8 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 222)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mailbox_9:


Clocks for NAVSS0_MAILBOX_9 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MAILBOX_9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 223)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_mcrc_0:


Clocks for NAVSS0_MCRC_0 Device
-------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MCRC_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 227)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------+-------------+
|   Clock ID | Name                  | Function    |
+============+=======================+=============+
|          0 | DEV_NAVSS0_MCRC_0_CLK | Input clock |
+------------+-----------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_modss:


Clocks for NAVSS0_MODSS Device
------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MODSS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 299)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_NAVSS0_MODSS_VD2CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_modss_intaggr_0:


Clocks for NAVSS0_MODSS_INTAGGR_0 Device
----------------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MODSS_INTAGGR_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 207)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_modss_intaggr_1:


Clocks for NAVSS0_MODSS_INTAGGR_1 Device
----------------------------------------

Device: :ref:`J721E_DEV_NAVSS0_MODSS_INTAGGR_1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 208)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_proxy_0:


Clocks for NAVSS0_PROXY_0 Device
--------------------------------

Device: :ref:`J721E_DEV_NAVSS0_PROXY_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 210)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_NAVSS0_PROXY_0_CLK_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_ringacc_0:


Clocks for NAVSS0_RINGACC_0 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_RINGACC_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 211)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------+-------------+
|   Clock ID | Name                         | Function    |
+============+==============================+=============+
|          0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | Input clock |
+------------+------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_spinlock_0:


Clocks for NAVSS0_SPINLOCK_0 Device
-----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_SPINLOCK_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 226)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------+-------------+
|   Clock ID | Name                      | Function    |
+============+===========================+=============+
|          0 | DEV_NAVSS0_SPINLOCK_0_CLK | Input clock |
+------------+---------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_tbu_0:


Clocks for NAVSS0_TBU_0 Device
------------------------------

Device: :ref:`J721E_DEV_NAVSS0_TBU_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 228)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_NAVSS0_TBU_0_CLK_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_tcu_0:


Clocks for NAVSS0_TCU_0 Device
------------------------------

Device: :ref:`J721E_DEV_NAVSS0_TCU_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 229)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_NAVSS0_TCU_0_CLK_CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_timermgr_0:


Clocks for NAVSS0_TIMERMGR_0 Device
-----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_TIMERMGR_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 230)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK     | Input clock |
+------------+------------------------------------+-------------+
|          1 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_timermgr_1:


Clocks for NAVSS0_TIMERMGR_1 Device
-----------------------------------

Device: :ref:`J721E_DEV_NAVSS0_TIMERMGR_1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 231)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK     | Input clock |
+------------+------------------------------------+-------------+
|          1 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_udmap_0:


Clocks for NAVSS0_UDMAP_0 Device
--------------------------------

Device: :ref:`J721E_DEV_NAVSS0_UDMAP_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 212)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | Input clock |
+------------+----------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_udmass:


Clocks for NAVSS0_UDMASS Device
-------------------------------

Device: :ref:`J721E_DEV_NAVSS0_UDMASS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 300)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_NAVSS0_UDMASS_VD2CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_udmass_intaggr_0:


Clocks for NAVSS0_UDMASS_INTAGGR_0 Device
-----------------------------------------

Device: :ref:`J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 209)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------+-------------+
|   Clock ID | Name                                | Function    |
+============+=====================================+=============+
|          0 | DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK | Input clock |
+------------+-------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss0_virtss:


Clocks for NAVSS0_VIRTSS Device
-------------------------------

Device: :ref:`J721E_DEV_NAVSS0_VIRTSS <soc_doc_j721e_public_devices_desc_device_list>` (ID = 301)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------+-------------+
|   Clock ID | Name                     | Function    |
+============+==========================+=============+
|          0 | DEV_NAVSS0_VIRTSS_VD2CLK | Input clock |
+------------+--------------------------+-------------+

.. _soc_doc_j721e_public_clks_navss512l_main_0:


Clocks for NAVSS512L_MAIN_0 Device
----------------------------------

Device: :ref:`J721E_DEV_NAVSS512L_MAIN_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 199)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+--------------+
|   Clock ID | Name                               | Function     |
+============+====================================+==============+
|          0 | DEV_NAVSS512L_MAIN_0_CPTS0_GENF3_0 | Output clock |
+------------+------------------------------------+--------------+
|          1 | DEV_NAVSS512L_MAIN_0_CPTS0_GENF2_0 | Output clock |
+------------+------------------------------------+--------------+

.. _soc_doc_j721e_public_clks_navss_mcu_j7_mcu_0:


Clocks for NAVSS_MCU_J7_MCU_0 Device
------------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist0:


Clocks for PBIST0 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist1:


Clocks for PBIST1 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist10:


Clocks for PBIST10 Device
-------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist2:


Clocks for PBIST2 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist3:


Clocks for PBIST3 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist4:


Clocks for PBIST4 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist5:


Clocks for PBIST5 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist6:


Clocks for PBIST6 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist7:


Clocks for PBIST7 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pbist9:


Clocks for PBIST9 Device
------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_pcie0:


Clocks for PCIE0 Device
-----------------------

Device: :ref:`J721E_DEV_PCIE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 239)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                                  |
+============+===============================================================================+===========================================================+
|          0 | DEV_PCIE0_PCIE_LANE1_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_PCIE0_PCIE_CBA_CLK                                                        | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_PCIE0_PCIE_LANE1_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK                                                  | Input muxed clock                                         |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          4 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          5 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          6 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_PCIE0_PCIE_LANE1_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_PCIE0_PCIE_LANE1_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_PCIE0_PCIE_LANE0_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_PCIE0_PCIE_LANE0_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_PCIE0_PCIE_LANE0_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_PCIE0_PCIE_PM_CLK                                                         | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_PCIE0_PCIE_LANE0_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_PCIE0_PCIE_LANE1_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_PCIE0_PCIE_LANE0_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_PCIE0_PCIE_LANE1_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         30 | DEV_PCIE0_PCIE_LANE0_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_pcie1:


Clocks for PCIE1 Device
-----------------------

Device: :ref:`J721E_DEV_PCIE1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 240)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                                  |
+============+===============================================================================+===========================================================+
|          0 | DEV_PCIE1_PCIE_LANE1_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_PCIE1_PCIE_CBA_CLK                                                        | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_PCIE1_PCIE_LANE1_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK                                                  | Input muxed clock                                         |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          4 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          5 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          6 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_PCIE1_PCIE_LANE1_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_PCIE1_PCIE_LANE1_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_PCIE1_PCIE_LANE0_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_PCIE1_PCIE_LANE0_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_PCIE1_PCIE_LANE0_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_PCIE1_PCIE_PM_CLK                                                         | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_PCIE1_PCIE_LANE0_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_PCIE1_PCIE_LANE1_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_PCIE1_PCIE_LANE0_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_PCIE1_PCIE_LANE1_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         30 | DEV_PCIE1_PCIE_LANE0_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_pcie2:


Clocks for PCIE2 Device
-----------------------

Device: :ref:`J721E_DEV_PCIE2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 241)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                                  |
+============+===============================================================================+===========================================================+
|          0 | DEV_PCIE2_PCIE_LANE1_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_PCIE2_PCIE_CBA_CLK                                                        | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_PCIE2_PCIE_LANE1_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK                                                  | Input muxed clock                                         |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          4 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          5 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          6 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_PCIE2_PCIE_LANE1_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_PCIE2_PCIE_LANE1_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_PCIE2_PCIE_LANE0_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_PCIE2_PCIE_LANE0_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_PCIE2_PCIE_LANE0_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_PCIE2_PCIE_PM_CLK                                                         | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_PCIE2_PCIE_LANE0_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_PCIE2_PCIE_LANE1_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_PCIE2_PCIE_LANE0_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_PCIE2_PCIE_LANE1_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         30 | DEV_PCIE2_PCIE_LANE0_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_pcie3:


Clocks for PCIE3 Device
-----------------------

Device: :ref:`J721E_DEV_PCIE3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 242)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                          | Function                                                  |
+============+===============================================================================+===========================================================+
|          0 | DEV_PCIE3_PCIE_LANE1_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_PCIE3_PCIE_CBA_CLK                                                        | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_PCIE3_PCIE_LANE1_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK                                                  | Input muxed clock                                         |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          4 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          5 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          6 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0    | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_PCIE3_PCIE_LANE1_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_PCIE3_PCIE_LANE1_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_PCIE3_PCIE_LANE0_REFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_PCIE3_PCIE_LANE0_TXMCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_PCIE3_PCIE_LANE0_TXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_PCIE3_PCIE_PM_CLK                                                         | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_PCIE3_PCIE_LANE0_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_PCIE3_PCIE_LANE1_RXFCLK                                                   | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_PCIE3_PCIE_LANE0_RXCLK                                                    | Input clock                                               |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_PCIE3_PCIE_LANE1_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+
|         30 | DEV_PCIE3_PCIE_LANE0_TXCLK                                                    | Output clock                                              |
+------------+-------------------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_pru_icssg0:


Clocks for PRU_ICSSG0 Device
----------------------------

Device: :ref:`J721E_DEV_PRU_ICSSG0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 119)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                             |
+============+=========================================================================+======================================================+
|          0 | DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I_0                                       | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          1 | DEV_PRU_ICSSG0_VCLK_CLK                                                 | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          2 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I_0                                       | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          3 | DEV_PRU_ICSSG0_IEP_CLK                                                  | Input muxed clock                                    |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          4 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          5 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          6 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          7 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          8 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|          9 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         10 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         11 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         12 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         13 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         14 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         15 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         16 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         17 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         18 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         19 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         20 | DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK                                          | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         21 | DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I_0                                       | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         22 | DEV_PRU_ICSSG0_UCLK_CLK                                                 | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         23 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I_0                                       | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         24 | DEV_PRU_ICSSG0_CORE_CLK                                                 | Input muxed clock                                    |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         25 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK        | Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         26 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK        | Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         27 | DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK                                        | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         28 | DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK                                         | Input clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         29 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O_0                                       | Output clock                                         |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         30 | DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O_0                                       | Output clock                                         |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+
|         31 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O_0                                       | Output clock                                         |
+------------+-------------------------------------------------------------------------+------------------------------------------------------+

.. _soc_doc_j721e_public_clks_pru_icssg1:


Clocks for PRU_ICSSG1 Device
----------------------------

Device: :ref:`J721E_DEV_PRU_ICSSG1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 120)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                    | Function                                                   |
+============+=========================================================================+============================================================+
|          0 | DEV_PRU_ICSSG1_SERDES0_RXCLK                                            | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK    | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK    | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I_0                                       | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_PRU_ICSSG1_VCLK_CLK                                                 | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I_0                                       | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_PRU_ICSSG1_SERDES0_RXFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_PRU_ICSSG1_IEP_CLK                                                  | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK         | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK        |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK                                          | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_PRU_ICSSG1_SERDES0_TXMCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_PRU_ICSSG1_SERDES0_REFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_PRU_ICSSG1_SERDES1_RXFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I_0                                       | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_PRU_ICSSG1_SERDES1_RXCLK                                            | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK    | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK    | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK  |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_PRU_ICSSG1_SERDES1_TXFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         42 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         43 | DEV_PRU_ICSSG1_SERDES1_TXMCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         44 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         45 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         46 | DEV_PRU_ICSSG1_SERDES0_TXFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         47 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         48 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         49 | DEV_PRU_ICSSG1_UCLK_CLK                                                 | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         50 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I_0                                       | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         51 | DEV_PRU_ICSSG1_SERDES1_REFCLK                                           | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         52 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         53 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK  | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         54 | DEV_PRU_ICSSG1_CORE_CLK                                                 | Input muxed clock                                          |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         55 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK        | Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK       |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         56 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK        | Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK       |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         57 | DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK                                        | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         58 | DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK                                         | Input clock                                                |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         59 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O_0                                       | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         60 | DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O_0                                       | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         61 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O_0                                       | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         62 | DEV_PRU_ICSSG1_SERDES0_TXCLK                                            | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+
|         63 | DEV_PRU_ICSSG1_SERDES1_TXCLK                                            | Output clock                                               |
+------------+-------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_psc0:


Clocks for PSC0 Device
----------------------

Device: :ref:`J721E_DEV_PSC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 133)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_PSC0_SLOW_CLK | Input clock |
+------------+-------------------+-------------+
|          1 | DEV_PSC0_CLK      | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_pulsar_sl_main_0:


Clocks for PULSAR_SL_MAIN_0 Device
----------------------------------

Device: :ref:`J721E_DEV_PULSAR_SL_MAIN_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 243)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_PULSAR_SL_MAIN_0_INTERFACE0_PHASE_0 | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_PULSAR_SL_MAIN_0_INTERFACE1_PHASE_0 | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_pulsar_sl_main_1:


Clocks for PULSAR_SL_MAIN_1 Device
----------------------------------

Device: :ref:`J721E_DEV_PULSAR_SL_MAIN_1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 244)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------+-------------+
|   Clock ID | Name                                    | Function    |
+============+=========================================+=============+
|          0 | DEV_PULSAR_SL_MAIN_1_INTERFACE0_PHASE_0 | Input clock |
+------------+-----------------------------------------+-------------+
|          1 | DEV_PULSAR_SL_MAIN_1_INTERFACE1_PHASE_0 | Input clock |
+------------+-----------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_pulsar_sl_mcu_0:


Clocks for PULSAR_SL_MCU_0 Device
---------------------------------

Device: :ref:`J721E_DEV_PULSAR_SL_MCU_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 249)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------+
|   Clock ID | Name                                                                                     | Function                                                            |
+============+==========================================================================================+=====================================================================+
|          0 | DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0                                                   | Input muxed clock                                                   |
+------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------+
|          1 | DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0 |
+------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------+
|          2 | DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0                                                   | Input muxed clock                                                   |
+------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------+
|          3 | DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0 |
+------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_r5fss0_core0:


Clocks for R5FSS0_CORE0 Device
------------------------------

Device: :ref:`J721E_DEV_R5FSS0_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 245)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS0_CORE0_CPU_CLK       | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_r5fss0_core1:


Clocks for R5FSS0_CORE1 Device
------------------------------

Device: :ref:`J721E_DEV_R5FSS0_CORE1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 246)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS0_CORE1_CPU_CLK       | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_r5fss0_introuter0:


Clocks for R5FSS0_INTROUTER0 Device
-----------------------------------

Device: :ref:`J721E_DEV_R5FSS0_INTROUTER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 134)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS0_INTROUTER0_INTR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_r5fss1_core0:


Clocks for R5FSS1_CORE0 Device
------------------------------

Device: :ref:`J721E_DEV_R5FSS1_CORE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 247)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS1_CORE0_CPU_CLK       | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_R5FSS1_CORE0_INTERFACE_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_r5fss1_core1:


Clocks for R5FSS1_CORE1 Device
------------------------------

Device: :ref:`J721E_DEV_R5FSS1_CORE1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 248)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS1_CORE1_CPU_CLK       | Input clock |
+------------+--------------------------------+-------------+
|          1 | DEV_R5FSS1_CORE1_INTERFACE_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_r5fss1_introuter0:


Clocks for R5FSS1_INTROUTER0 Device
-----------------------------------

Device: :ref:`J721E_DEV_R5FSS1_INTROUTER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 135)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------+-------------+
|   Clock ID | Name                           | Function    |
+============+================================+=============+
|          0 | DEV_R5FSS1_INTROUTER0_INTR_CLK | Input clock |
+------------+--------------------------------+-------------+

.. _soc_doc_j721e_public_clks_rti0:


Clocks for RTI0 Device
----------------------

Device: :ref:`J721E_DEV_RTI0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 252)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+-----------------------------------------------+
|   Clock ID | Name                                                               | Function                                      |
+============+====================================================================+===============================================+
|          0 | DEV_RTI0_VBUSP_CLK                                                 | Input clock                                   |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          1 | DEV_RTI0_RTI_CLK                                                   | Input muxed clock                             |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          3 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          4 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          5 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI0_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+

.. _soc_doc_j721e_public_clks_rti1:


Clocks for RTI1 Device
----------------------

Device: :ref:`J721E_DEV_RTI1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 253)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+-----------------------------------------------+
|   Clock ID | Name                                                               | Function                                      |
+============+====================================================================+===============================================+
|          0 | DEV_RTI1_VBUSP_CLK                                                 | Input clock                                   |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          1 | DEV_RTI1_RTI_CLK                                                   | Input muxed clock                             |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          3 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          4 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          5 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+
|          9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI1_RTI_CLK |
+------------+--------------------------------------------------------------------+-----------------------------------------------+

.. _soc_doc_j721e_public_clks_rti15:


Clocks for RTI15 Device
-----------------------

Device: :ref:`J721E_DEV_RTI15 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 257)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI15_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI15_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI15_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti16:


Clocks for RTI16 Device
-----------------------

Device: :ref:`J721E_DEV_RTI16 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 256)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI16_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI16_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI16_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti24:


Clocks for RTI24 Device
-----------------------

Device: :ref:`J721E_DEV_RTI24 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 254)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI24_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI24_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI24_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti25:


Clocks for RTI25 Device
-----------------------

Device: :ref:`J721E_DEV_RTI25 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 255)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI25_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI25_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI25_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti28:


Clocks for RTI28 Device
-----------------------

Device: :ref:`J721E_DEV_RTI28 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 258)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI28_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI28_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI28_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti29:


Clocks for RTI29 Device
-----------------------

Device: :ref:`J721E_DEV_RTI29 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 259)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI29_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI29_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI29_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti30:


Clocks for RTI30 Device
-----------------------

Device: :ref:`J721E_DEV_RTI30 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 260)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI30_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI30_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI30_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_rti31:


Clocks for RTI31 Device
-----------------------

Device: :ref:`J721E_DEV_RTI31 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 261)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+------------------------------------------------+
|   Clock ID | Name                                                                | Function                                       |
+============+=====================================================================+================================================+
|          0 | DEV_RTI31_VBUSP_CLK                                                 | Input clock                                    |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          1 | DEV_RTI31_RTI_CLK                                                   | Input muxed clock                              |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          2 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          3 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          4 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          5 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          6 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          7 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          8 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+
|          9 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                | Parent input clock option to DEV_RTI31_RTI_CLK |
+------------+---------------------------------------------------------------------+------------------------------------------------+

.. _soc_doc_j721e_public_clks_sa2_ul0:


Clocks for SA2_UL0 Device
-------------------------

Device: :ref:`J721E_DEV_SA2_UL0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 264)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_SA2_UL0_X2_CLK     | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_SA2_UL0_PKA_IN_CLK | Input clock |
+------------+------------------------+-------------+
|          2 | DEV_SA2_UL0_X1_CLK     | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_serdes_10g0:


Clocks for SERDES_10G0 Device
-----------------------------

Device: :ref:`J721E_DEV_SERDES_10G0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 297)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|   Clock ID | Name                                                                  | Function                                                  |
+============+=======================================================================+===========================================================+
|          0 | DEV_SERDES_10G0_IP1_LN3_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          1 | DEV_SERDES_10G0_CLK                                                   | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          2 | DEV_SERDES_10G0_IP3_LN2_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          3 | DEV_SERDES_10G0_IP1_LN2_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          4 | DEV_SERDES_10G0_IP1_LN0_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          5 | DEV_SERDES_10G0_IP3_LN1_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          6 | DEV_SERDES_10G0_IP3_LN3_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          7 | DEV_SERDES_10G0_IP3_LN0_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          8 | DEV_SERDES_10G0_IP1_LN1_TXCLK                                         | Input clock                                               |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|          9 | DEV_SERDES_10G0_CORE_REF_CLK                                          | Input muxed clock                                         |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         10 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         11 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         12 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         13 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         14 | DEV_SERDES_10G0_IP1_LN1_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         15 | DEV_SERDES_10G0_IP1_LN2_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         16 | DEV_SERDES_10G0_IP3_LN1_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         17 | DEV_SERDES_10G0_IP1_LN0_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         18 | DEV_SERDES_10G0_IP1_LN3_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         19 | DEV_SERDES_10G0_IP3_LN3_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         20 | DEV_SERDES_10G0_IP3_LN1_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         21 | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         22 | DEV_SERDES_10G0_IP3_LN3_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         23 | DEV_SERDES_10G0_IP3_LN2_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         24 | DEV_SERDES_10G0_IP1_LN0_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         25 | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         26 | DEV_SERDES_10G0_IP3_LN1_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         27 | DEV_SERDES_10G0_IP3_LN0_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         28 | DEV_SERDES_10G0_IP1_LN1_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         29 | DEV_SERDES_10G0_IP1_LN1_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         30 | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         31 | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         32 | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         33 | DEV_SERDES_10G0_IP3_LN1_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         34 | DEV_SERDES_10G0_IP3_LN0_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         35 | DEV_SERDES_10G0_IP1_LN3_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         36 | DEV_SERDES_10G0_IP3_LN0_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         37 | DEV_SERDES_10G0_IP3_LN2_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         38 | DEV_SERDES_10G0_IP1_LN0_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         39 | DEV_SERDES_10G0_IP1_LN0_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         40 | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         41 | DEV_SERDES_10G0_IP1_LN1_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         42 | DEV_SERDES_10G0_IP3_LN0_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         43 | DEV_SERDES_10G0_REF_OUT_CLK                                           | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         44 | DEV_SERDES_10G0_IP3_LN1_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         45 | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         46 | DEV_SERDES_10G0_IP1_LN0_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         47 | DEV_SERDES_10G0_IP3_LN2_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         48 | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         49 | DEV_SERDES_10G0_IP3_LN2_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         50 | DEV_SERDES_10G0_IP1_LN2_REFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         51 | DEV_SERDES_10G0_IP3_LN2_TXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         52 | DEV_SERDES_10G0_IP3_LN0_TXMCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         53 | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                        | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+
|         54 | DEV_SERDES_10G0_IP1_LN1_RXCLK                                         | Output clock                                              |
+------------+-----------------------------------------------------------------------+-----------------------------------------------------------+

.. _soc_doc_j721e_public_clks_serdes_16g0:


Clocks for SERDES_16G0 Device
-----------------------------

Device: :ref:`J721E_DEV_SERDES_16G0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 292)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                                   |
+============+========================================================================+============================================================+
|          0 | DEV_SERDES_16G0_CORE_REF1_CLK                                          | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_SERDES_16G0_CLK                                                    | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_SERDES_16G0_IP1_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_SERDES_16G0_IP2_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_SERDES_16G0_IP3_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_SERDES_16G0_IP2_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_SERDES_16G0_IP1_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_SERDES_16G0_CORE_REF_CLK                                           | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_SERDES_16G0_IP2_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_SERDES_16G0_IP1_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_SERDES_16G0_IP3_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_SERDES_16G0_IP3_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_SERDES_16G0_IP1_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_SERDES_16G0_IP2_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_SERDES_16G0_IP2_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_SERDES_16G0_IP1_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_SERDES_16G0_IP3_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_SERDES_16G0_IP1_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_SERDES_16G0_IP1_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_SERDES_16G0_IP3_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_SERDES_16G0_IP3_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_SERDES_16G0_IP2_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_SERDES_16G0_IP2_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_SERDES_16G0_IP1_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_SERDES_16G0_REF_OUT_CLK                                            | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_SERDES_16G0_REF1_OUT_CLK                                           | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_SERDES_16G0_IP1_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_SERDES_16G0_IP1_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_SERDES_16G0_IP2_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_SERDES_16G0_IP2_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_SERDES_16G0_IP2_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_SERDES_16G0_IP2_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_SERDES_16G0_IP1_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         42 | DEV_SERDES_16G0_IP2_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         43 | DEV_SERDES_16G0_IP1_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         49 | DEV_SERDES_16G0_CMN_REFCLK1_M_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         57 | DEV_SERDES_16G0_CMN_REFCLK1_P_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_serdes_16g1:


Clocks for SERDES_16G1 Device
-----------------------------

Device: :ref:`J721E_DEV_SERDES_16G1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 293)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                                   |
+============+========================================================================+============================================================+
|          0 | DEV_SERDES_16G1_CORE_REF1_CLK                                          | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_SERDES_16G1_CLK                                                    | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_SERDES_16G1_IP1_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_SERDES_16G1_IP2_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_SERDES_16G1_IP4_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_SERDES_16G1_IP4_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_SERDES_16G1_IP3_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_SERDES_16G1_IP2_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_SERDES_16G1_IP1_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_SERDES_16G1_CORE_REF_CLK                                           | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_SERDES_16G1_IP2_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_SERDES_16G1_IP1_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_SERDES_16G1_IP4_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_SERDES_16G1_IP3_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_SERDES_16G1_IP3_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_SERDES_16G1_IP1_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_SERDES_16G1_IP2_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_SERDES_16G1_IP2_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_SERDES_16G1_IP1_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_SERDES_16G1_IP3_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_SERDES_16G1_IP1_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_SERDES_16G1_IP1_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_SERDES_16G1_IP4_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_SERDES_16G1_IP3_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_SERDES_16G1_IP4_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_SERDES_16G1_IP3_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_SERDES_16G1_IP4_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_SERDES_16G1_IP2_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_SERDES_16G1_IP2_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_SERDES_16G1_IP1_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_SERDES_16G1_REF_OUT_CLK                                            | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_SERDES_16G1_REF1_OUT_CLK                                           | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_SERDES_16G1_IP4_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         42 | DEV_SERDES_16G1_IP1_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         43 | DEV_SERDES_16G1_IP1_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         44 | DEV_SERDES_16G1_IP4_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         45 | DEV_SERDES_16G1_IP4_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         46 | DEV_SERDES_16G1_IP2_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         47 | DEV_SERDES_16G1_IP2_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         48 | DEV_SERDES_16G1_IP4_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         49 | DEV_SERDES_16G1_IP2_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         50 | DEV_SERDES_16G1_IP2_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         51 | DEV_SERDES_16G1_IP1_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         52 | DEV_SERDES_16G1_IP2_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         53 | DEV_SERDES_16G1_IP4_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         54 | DEV_SERDES_16G1_IP1_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         55 | DEV_SERDES_16G1_IP4_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         60 | DEV_SERDES_16G1_CMN_REFCLK1_M_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         67 | DEV_SERDES_16G1_CMN_REFCLK1_P_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_serdes_16g2:


Clocks for SERDES_16G2 Device
-----------------------------

Device: :ref:`J721E_DEV_SERDES_16G2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 294)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                                   |
+============+========================================================================+============================================================+
|          0 | DEV_SERDES_16G2_CORE_REF1_CLK                                          | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_SERDES_16G2_CLK                                                    | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_SERDES_16G2_IP2_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_SERDES_16G2_IP4_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_SERDES_16G2_IP4_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_SERDES_16G2_IP3_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_SERDES_16G2_IP2_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_SERDES_16G2_CORE_REF_CLK                                           | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_SERDES_16G2_IP2_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_SERDES_16G2_IP4_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_SERDES_16G2_IP3_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         19 | DEV_SERDES_16G2_IP3_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_SERDES_16G2_IP2_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_SERDES_16G2_IP2_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_SERDES_16G2_IP3_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_SERDES_16G2_IP4_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_SERDES_16G2_IP3_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_SERDES_16G2_IP4_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_SERDES_16G2_IP3_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_SERDES_16G2_IP4_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_SERDES_16G2_IP2_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_SERDES_16G2_IP2_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_SERDES_16G2_REF_OUT_CLK                                            | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         32 | DEV_SERDES_16G2_REF1_OUT_CLK                                           | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         33 | DEV_SERDES_16G2_IP4_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         34 | DEV_SERDES_16G2_IP4_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         35 | DEV_SERDES_16G2_IP4_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         36 | DEV_SERDES_16G2_IP2_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         37 | DEV_SERDES_16G2_IP2_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         38 | DEV_SERDES_16G2_IP4_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         39 | DEV_SERDES_16G2_IP2_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_SERDES_16G2_IP2_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         41 | DEV_SERDES_16G2_IP2_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         42 | DEV_SERDES_16G2_IP4_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         43 | DEV_SERDES_16G2_IP4_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         51 | DEV_SERDES_16G2_CMN_REFCLK1_M_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         61 | DEV_SERDES_16G2_CMN_REFCLK1_P_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_serdes_16g3:


Clocks for SERDES_16G3 Device
-----------------------------

Device: :ref:`J721E_DEV_SERDES_16G3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 295)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|   Clock ID | Name                                                                   | Function                                                   |
+============+========================================================================+============================================================+
|          0 | DEV_SERDES_16G3_CORE_REF1_CLK                                          | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          1 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          2 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          3 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          4 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          5 | DEV_SERDES_16G3_CLK                                                    | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          6 | DEV_SERDES_16G3_IP2_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          7 | DEV_SERDES_16G3_IP3_LN1_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          8 | DEV_SERDES_16G3_IP2_LN0_TXCLK                                          | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|          9 | DEV_SERDES_16G3_CORE_REF_CLK                                           | Input muxed clock                                          |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         10 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT            | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         11 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT             | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         12 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         13 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK  | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK  |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         14 | DEV_SERDES_16G3_IP2_LN0_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         15 | DEV_SERDES_16G3_IP3_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         16 | DEV_SERDES_16G3_IP3_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         17 | DEV_SERDES_16G3_IP2_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         18 | DEV_SERDES_16G3_IP2_LN1_TXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         20 | DEV_SERDES_16G3_IP3_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         21 | DEV_SERDES_16G3_IP3_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         22 | DEV_SERDES_16G3_IP3_LN1_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         23 | DEV_SERDES_16G3_IP2_LN1_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         24 | DEV_SERDES_16G3_IP2_LN0_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         25 | DEV_SERDES_16G3_REF_OUT_CLK                                            | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         26 | DEV_SERDES_16G3_REF1_OUT_CLK                                           | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         27 | DEV_SERDES_16G3_IP2_LN1_RXFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         28 | DEV_SERDES_16G3_IP2_LN1_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         29 | DEV_SERDES_16G3_IP2_LN0_REFCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         30 | DEV_SERDES_16G3_IP2_LN0_TXMCLK                                         | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         31 | DEV_SERDES_16G3_IP2_LN0_RXCLK                                          | Output clock                                               |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         40 | DEV_SERDES_16G3_CMN_REFCLK1_M_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+
|         51 | DEV_SERDES_16G3_CMN_REFCLK1_P_0                                        | Input clock                                                |
+------------+------------------------------------------------------------------------+------------------------------------------------------------+

.. _soc_doc_j721e_public_clks_stm0:


Clocks for STM0 Device
----------------------

Device: :ref:`J721E_DEV_STM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 29)

Following is a mapping of Clocks IDs to function:

+------------+--------------------+-------------+
|   Clock ID | Name               | Function    |
+============+====================+=============+
|          0 | DEV_STM0_VBUSP_CLK | Input clock |
+------------+--------------------+-------------+
|          1 | DEV_STM0_CORE_CLK  | Input clock |
+------------+--------------------+-------------+
|          2 | DEV_STM0_ATB_CLK   | Input clock |
+------------+--------------------+-------------+

.. _soc_doc_j721e_public_clks_timer0:


Clocks for TIMER0 Device
------------------------

Device: :ref:`J721E_DEV_TIMER0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 49)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                        | Function                                               |
+============+=============================================================================+========================================================+
|          0 | DEV_TIMER0_TIMER_HCLK_CLK                                                   | Input clock                                            |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER0_TIMER_TCLK_CLK                                                   | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         18 | DEV_TIMER0_TIMER_PWM_0                                                      | Output clock                                           |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer1:


Clocks for TIMER1 Device
------------------------

Device: :ref:`J721E_DEV_TIMER1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 50)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_TIMER1_TIMER_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER1_TIMER_TCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1            | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM_0 | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer10:


Clocks for TIMER10 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER10 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 60)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_TIMER10_TIMER_HCLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER10_TIMER_TCLK_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_TIMER10_TIMER_PWM_0                                                      | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer11:


Clocks for TIMER11 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER11 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 62)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                |
+============+======================================================================+=========================================================+
|          0 | DEV_TIMER11_TIMER_HCLK_CLK                                           | Input clock                                             |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER11_TIMER_TCLK_CLK                                           | Input muxed clock                                       |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11            | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM_0 | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer12:


Clocks for TIMER12 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER12 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 63)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_TIMER12_TIMER_HCLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER12_TIMER_TCLK_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_TIMER12_TIMER_PWM_0                                                      | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer13:


Clocks for TIMER13 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER13 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 64)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                |
+============+======================================================================+=========================================================+
|          0 | DEV_TIMER13_TIMER_HCLK_CLK                                           | Input clock                                             |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER13_TIMER_TCLK_CLK                                           | Input muxed clock                                       |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13            | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM_0 | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer14:


Clocks for TIMER14 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER14 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 65)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_TIMER14_TIMER_HCLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER14_TIMER_TCLK_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_TIMER14_TIMER_PWM_0                                                      | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer15:


Clocks for TIMER15 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER15 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 66)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                |
+============+======================================================================+=========================================================+
|          0 | DEV_TIMER15_TIMER_HCLK_CLK                                           | Input clock                                             |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER15_TIMER_TCLK_CLK                                           | Input muxed clock                                       |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15            | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM_0 | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer16:


Clocks for TIMER16 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER16 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 67)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_TIMER16_TIMER_HCLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER16_TIMER_TCLK_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_TIMER16_TIMER_PWM_0                                                      | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer17:


Clocks for TIMER17 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER17 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 68)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                |
+============+======================================================================+=========================================================+
|          0 | DEV_TIMER17_TIMER_HCLK_CLK                                           | Input clock                                             |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER17_TIMER_TCLK_CLK                                           | Input muxed clock                                       |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17            | Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM_0 | Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer18:


Clocks for TIMER18 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER18 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 69)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                         | Function                                                |
+============+==============================================================================+=========================================================+
|          0 | DEV_TIMER18_TIMER_HCLK_CLK                                                   | Input clock                                             |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER18_TIMER_TCLK_CLK                                                   | Input muxed clock                                       |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_TIMER18_TIMER_PWM_0                                                      | Output clock                                            |
+------------+------------------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer19:


Clocks for TIMER19 Device
-------------------------

Device: :ref:`J721E_DEV_TIMER19 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 70)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                                 | Function                                                |
+============+======================================================================+=========================================================+
|          0 | DEV_TIMER19_TIMER_HCLK_CLK                                           | Input clock                                             |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_TIMER19_TIMER_TCLK_CLK                                           | Input muxed clock                                       |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19            | Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM_0 | Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK |
+------------+----------------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer2:


Clocks for TIMER2 Device
------------------------

Device: :ref:`J721E_DEV_TIMER2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 51)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                        | Function                                               |
+============+=============================================================================+========================================================+
|          0 | DEV_TIMER2_TIMER_HCLK_CLK                                                   | Input clock                                            |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER2_TIMER_TCLK_CLK                                                   | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         18 | DEV_TIMER2_TIMER_PWM_0                                                      | Output clock                                           |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer3:


Clocks for TIMER3 Device
------------------------

Device: :ref:`J721E_DEV_TIMER3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 52)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_TIMER3_TIMER_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER3_TIMER_TCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3            | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM_0 | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer4:


Clocks for TIMER4 Device
------------------------

Device: :ref:`J721E_DEV_TIMER4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 53)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                        | Function                                               |
+============+=============================================================================+========================================================+
|          0 | DEV_TIMER4_TIMER_HCLK_CLK                                                   | Input clock                                            |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER4_TIMER_TCLK_CLK                                                   | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         18 | DEV_TIMER4_TIMER_PWM_0                                                      | Output clock                                           |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer5:


Clocks for TIMER5 Device
------------------------

Device: :ref:`J721E_DEV_TIMER5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 54)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_TIMER5_TIMER_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER5_TIMER_TCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5            | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM_0 | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer6:


Clocks for TIMER6 Device
------------------------

Device: :ref:`J721E_DEV_TIMER6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 55)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                        | Function                                               |
+============+=============================================================================+========================================================+
|          0 | DEV_TIMER6_TIMER_HCLK_CLK                                                   | Input clock                                            |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER6_TIMER_TCLK_CLK                                                   | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         18 | DEV_TIMER6_TIMER_PWM_0                                                      | Output clock                                           |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer7:


Clocks for TIMER7 Device
------------------------

Device: :ref:`J721E_DEV_TIMER7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 57)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_TIMER7_TIMER_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER7_TIMER_TCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7            | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM_0 | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer8:


Clocks for TIMER8 Device
------------------------

Device: :ref:`J721E_DEV_TIMER8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 58)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                                        | Function                                               |
+============+=============================================================================+========================================================+
|          0 | DEV_TIMER8_TIMER_HCLK_CLK                                                   | Input clock                                            |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER8_TIMER_TCLK_CLK                                                   | Input muxed clock                                      |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                    | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                     | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK          | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                    | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|          9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                    | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                  | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK          | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK        | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK          | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0             | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0             | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0             | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK         | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+
|         18 | DEV_TIMER8_TIMER_PWM_0                                                      | Output clock                                           |
+------------+-----------------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timer9:


Clocks for TIMER9 Device
------------------------

Device: :ref:`J721E_DEV_TIMER9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 59)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|   Clock ID | Name                                                               | Function                                               |
+============+====================================================================+========================================================+
|          0 | DEV_TIMER9_TIMER_HCLK_CLK                                          | Input clock                                            |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          1 | DEV_TIMER9_TIMER_TCLK_CLK                                          | Input muxed clock                                      |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          2 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9            | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+
|          3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM_0 | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
+------------+--------------------------------------------------------------------+--------------------------------------------------------+

.. _soc_doc_j721e_public_clks_timesync_intrtr0:


Clocks for TIMESYNC_INTRTR0 Device
----------------------------------

Device: :ref:`J721E_DEV_TIMESYNC_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 136)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------------+-------------+
|   Clock ID | Name                          | Function    |
+============+===============================+=============+
|          0 | DEV_TIMESYNC_INTRTR0_INTR_CLK | Input clock |
+------------+-------------------------------+-------------+

.. _soc_doc_j721e_public_clks_uart0:


Clocks for UART0 Device
-----------------------

Device: :ref:`J721E_DEV_UART0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 146)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART0_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART0_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart1:


Clocks for UART1 Device
-----------------------

Device: :ref:`J721E_DEV_UART1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 278)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART1_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART1_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart2:


Clocks for UART2 Device
-----------------------

Device: :ref:`J721E_DEV_UART2 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 279)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART2_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART2_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart3:


Clocks for UART3 Device
-----------------------

Device: :ref:`J721E_DEV_UART3 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 280)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART3_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART3_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart4:


Clocks for UART4 Device
-----------------------

Device: :ref:`J721E_DEV_UART4 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 281)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART4_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART4_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart5:


Clocks for UART5 Device
-----------------------

Device: :ref:`J721E_DEV_UART5 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 282)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART5_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART5_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart6:


Clocks for UART6 Device
-----------------------

Device: :ref:`J721E_DEV_UART6 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 283)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART6_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART6_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart7:


Clocks for UART7 Device
-----------------------

Device: :ref:`J721E_DEV_UART7 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 284)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART7_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART7_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart8:


Clocks for UART8 Device
-----------------------

Device: :ref:`J721E_DEV_UART8 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 285)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART8_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART8_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_uart9:


Clocks for UART9 Device
-----------------------

Device: :ref:`J721E_DEV_UART9 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 286)

Following is a mapping of Clocks IDs to function:

+------------+---------------------+-------------+
|   Clock ID | Name                | Function    |
+============+=====================+=============+
|          0 | DEV_UART9_FCLK_CLK  | Input clock |
+------------+---------------------+-------------+
|          1 | DEV_UART9_VBUSP_CLK | Input clock |
+------------+---------------------+-------------+

.. _soc_doc_j721e_public_clks_ufs0:


Clocks for UFS0 Device
----------------------

Device: :ref:`J721E_DEV_UFS0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 277)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|   Clock ID | Name                                                                | Function                                              |
+============+=====================================================================+=======================================================+
|          0 | DEV_UFS0_UFSHCI_HCLK_CLK                                            | Input clock                                           |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          1 | DEV_UFS0_UFSHCI_MCLK_CLK                                            | Input muxed clock                                     |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          2 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT             | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          3 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT              | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          4 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          5 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT             | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+
|          6 | DEV_UFS0_UFSHCI_MPHY_REFCLK_0                                       | Output clock                                          |
+------------+---------------------------------------------------------------------+-------------------------------------------------------+

.. _soc_doc_j721e_public_clks_usb0:


Clocks for USB0 Device
----------------------

Device: :ref:`J721E_DEV_USB0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 288)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                          | Function                                                |
+============+===============================================================+=========================================================+
|          0 | DEV_USB0_PIPE_REFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK | Parent input clock option to DEV_USB0_PIPE_REFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK | Parent input clock option to DEV_USB0_PIPE_REFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_USB0_CLK_LPM_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_USB0_BUF_CLK                                              | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_USB0_USB2_APB_PCLK_CLK                                    | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_USB0_PIPE_RXCLK                                           | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK   | Parent input clock option to DEV_USB0_PIPE_RXCLK        |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK   | Parent input clock option to DEV_USB0_PIPE_RXCLK        |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_USB0_PIPE_TXMCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB0_PIPE_TXMCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB0_PIPE_TXMCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_USB0_PIPE_RXFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB0_PIPE_RXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB0_PIPE_RXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_USB0_USB2_REFCLOCK_CLK                                    | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT     | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT      | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_USB0_PCLK_CLK                                             | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         19 | DEV_USB0_ACLK_CLK                                             | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         20 | DEV_USB0_PIPE_TXFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         21 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB0_PIPE_TXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         22 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB0_PIPE_TXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         23 | DEV_USB0_PIPE_TXCLK                                           | Output clock                                            |
+------------+---------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_usb1:


Clocks for USB1 Device
----------------------

Device: :ref:`J721E_DEV_USB1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 289)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------------------------------------+---------------------------------------------------------+
|   Clock ID | Name                                                          | Function                                                |
+============+===============================================================+=========================================================+
|          0 | DEV_USB1_PIPE_REFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          1 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK | Parent input clock option to DEV_USB1_PIPE_REFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          2 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK | Parent input clock option to DEV_USB1_PIPE_REFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          3 | DEV_USB1_CLK_LPM_CLK                                          | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          4 | DEV_USB1_BUF_CLK                                              | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          5 | DEV_USB1_USB2_APB_PCLK_CLK                                    | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          6 | DEV_USB1_PIPE_RXCLK                                           | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          7 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK   | Parent input clock option to DEV_USB1_PIPE_RXCLK        |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          8 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK   | Parent input clock option to DEV_USB1_PIPE_RXCLK        |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|          9 | DEV_USB1_PIPE_TXMCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         10 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB1_PIPE_TXMCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         11 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB1_PIPE_TXMCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         12 | DEV_USB1_PIPE_RXFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         13 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB1_PIPE_RXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         14 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB1_PIPE_RXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         15 | DEV_USB1_USB2_REFCLOCK_CLK                                    | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         16 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT     | Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         17 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT      | Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         18 | DEV_USB1_PCLK_CLK                                             | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         19 | DEV_USB1_ACLK_CLK                                             | Input clock                                             |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         20 | DEV_USB1_PIPE_TXFCLK                                          | Input muxed clock                                       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         21 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB1_PIPE_TXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         22 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB1_PIPE_TXFCLK       |
+------------+---------------------------------------------------------------+---------------------------------------------------------+
|         23 | DEV_USB1_PIPE_TXCLK                                           | Output clock                                            |
+------------+---------------------------------------------------------------+---------------------------------------------------------+

.. _soc_doc_j721e_public_clks_vpac_top_main_0:


Clocks for VPAC_TOP_MAIN_0 Device
---------------------------------

Device: :ref:`J721E_DEV_VPAC_TOP_MAIN_0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 290)

Following is a mapping of Clocks IDs to function:

+------------+---------------------------------+-------------+
|   Clock ID | Name                            | Function    |
+============+=================================+=============+
|          0 | DEV_VPAC_TOP_MAIN_0_CLK         | Input clock |
+------------+---------------------------------+-------------+
|          1 | DEV_VPAC_TOP_MAIN_0_PLL_DCO_CLK | Input clock |
+------------+---------------------------------+-------------+

.. _soc_doc_j721e_public_clks_vpfe0:


Clocks for VPFE0 Device
-----------------------

Device: :ref:`J721E_DEV_VPFE0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 291)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_VPFE0_CCD_PCLK_CLK | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_VPFE0_VPFE_CLK     | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkupmcu2main_vd:


Clocks for WKUPMCU2MAIN_VD Device
---------------------------------

**This device has no defined clocks.**

.. _soc_doc_j721e_public_clks_wkup_ddpa0:


Clocks for WKUP_DDPA0 Device
----------------------------

Device: :ref:`J721E_DEV_WKUP_DDPA0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 145)

Following is a mapping of Clocks IDs to function:

+------------+-------------------------+-------------+
|   Clock ID | Name                    | Function    |
+============+=========================+=============+
|          0 | DEV_WKUP_DDPA0_DDPA_CLK | Input clock |
+------------+-------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_esm0:


Clocks for WKUP_ESM0 Device
---------------------------

Device: :ref:`J721E_DEV_WKUP_ESM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 99)

Following is a mapping of Clocks IDs to function:

+------------+-------------------+-------------+
|   Clock ID | Name              | Function    |
+============+===================+=============+
|          0 | DEV_WKUP_ESM0_CLK | Input clock |
+------------+-------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_gpio0:


Clocks for WKUP_GPIO0 Device
----------------------------

Device: :ref:`J721E_DEV_WKUP_GPIO0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 113)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_WKUP_GPIO0_MMR_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_gpio1:


Clocks for WKUP_GPIO1 Device
----------------------------

Device: :ref:`J721E_DEV_WKUP_GPIO1 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 114)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_WKUP_GPIO1_MMR_CLK | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_gpiomux_intrtr0:


Clocks for WKUP_GPIOMUX_INTRTR0 Device
--------------------------------------

Device: :ref:`J721E_DEV_WKUP_GPIOMUX_INTRTR0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 137)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------+-------------+
|   Clock ID | Name                              | Function    |
+============+===================================+=============+
|          0 | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK | Input clock |
+------------+-----------------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_i2c0:


Clocks for WKUP_I2C0 Device
---------------------------

Device: :ref:`J721E_DEV_WKUP_I2C0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 197)

Following is a mapping of Clocks IDs to function:

+------------+-----------------------------------------------------------------+------------------------------------------------------+
|   Clock ID | Name                                                            | Function                                             |
+============+=================================================================+======================================================+
|          0 | DEV_WKUP_I2C0_PISYS_CLK                                         | Input muxed clock                                    |
+------------+-----------------------------------------------------------------+------------------------------------------------------+
|          1 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK |
+------------+-----------------------------------------------------------------+------------------------------------------------------+
|          2 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT          | Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK |
+------------+-----------------------------------------------------------------+------------------------------------------------------+
|          3 | DEV_WKUP_I2C0_PISCL_0                                           | Input clock                                          |
+------------+-----------------------------------------------------------------+------------------------------------------------------+
|          4 | DEV_WKUP_I2C0_CLK                                               | Input clock                                          |
+------------+-----------------------------------------------------------------+------------------------------------------------------+
|          5 | DEV_WKUP_I2C0_PORSCL_0                                          | Output clock                                         |
+------------+-----------------------------------------------------------------+------------------------------------------------------+

.. _soc_doc_j721e_public_clks_wkup_porz_sync0:


Clocks for WKUP_PORZ_SYNC0 Device
---------------------------------

Device: :ref:`J721E_DEV_WKUP_PORZ_SYNC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 132)

Following is a mapping of Clocks IDs to function:

+------------+------------------------------------+-------------+
|   Clock ID | Name                               | Function    |
+============+====================================+=============+
|          0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | Input clock |
+------------+------------------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_psc0:


Clocks for WKUP_PSC0 Device
---------------------------

Device: :ref:`J721E_DEV_WKUP_PSC0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 138)

Following is a mapping of Clocks IDs to function:

+------------+------------------------+-------------+
|   Clock ID | Name                   | Function    |
+============+========================+=============+
|          0 | DEV_WKUP_PSC0_SLOW_CLK | Input clock |
+------------+------------------------+-------------+
|          1 | DEV_WKUP_PSC0_CLK      | Input clock |
+------------+------------------------+-------------+

.. _soc_doc_j721e_public_clks_wkup_uart0:


Clocks for WKUP_UART0 Device
----------------------------

Device: :ref:`J721E_DEV_WKUP_UART0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 287)

Following is a mapping of Clocks IDs to function:

+------------+--------------------------------------------------------+------------------------------------------------------+
|   Clock ID | Name                                                   | Function                                             |
+============+========================================================+======================================================+
|          0 | DEV_WKUP_UART0_FCLK_CLK                                | Input muxed clock                                    |
+------------+--------------------------------------------------------+------------------------------------------------------+
|          1 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0  | Parent input clock option to DEV_WKUP_UART0_FCLK_CLK |
+------------+--------------------------------------------------------+------------------------------------------------------+
|          2 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_WKUP_UART0_FCLK_CLK |
+------------+--------------------------------------------------------+------------------------------------------------------+
|          3 | DEV_WKUP_UART0_VBUSP_CLK                               | Input clock                                          |
+------------+--------------------------------------------------------+------------------------------------------------------+

.. _soc_doc_j721e_public_clks_wkup_vtm0:


Clocks for WKUP_VTM0 Device
---------------------------

Device: :ref:`J721E_DEV_WKUP_VTM0 <soc_doc_j721e_public_devices_desc_device_list>` (ID = 154)

Following is a mapping of Clocks IDs to function:

+------------+----------------------------+-------------+
|   Clock ID | Name                       | Function    |
+============+============================+=============+
|          0 | DEV_WKUP_VTM0_FIX_REF2_CLK | Input clock |
+------------+----------------------------+-------------+
|          1 | DEV_WKUP_VTM0_VBUSP_CLK    | Input clock |
+------------+----------------------------+-------------+
|          2 | DEV_WKUP_VTM0_FIX_REF_CLK  | Input clock |
+------------+----------------------------+-------------+

