[^:]*: Assembler messages:
[^:]*:3: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20'
[^:]*:4: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:5: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:6: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0'
[^:]*:7: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0'
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:18: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:20: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmlat.f16 q0,q1,q2,#0'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmla.f16 q0,q1,q2,#0'
